Re: [PATCH] hw/timer/a9gtimer: Clear pending interrupt, after the clear of Event flag

[Václav Vanc]

On 6/26/20 4:46 PM, Peter Maydell wrote:
> On Tue, 16 Jun 2020 at 08:04, Václav Vanc <vav@sysgo.com> wrote:
> > On 6/15/20 1:04 PM, Peter Maydell wrote:
> > We must distinguish between two cases:
> > 1, Auto-increment is disabled.
> > I just run some test on SABRE Lite (i.MX6) board.
> > I had auto-increment disabled, I verified, that GIC is configured for
> > Edge interrupts. Once count went past the compare value I got the
> > interrupt. I did not touch Timer registers, just signal EOI to GIC and
> > surprisingly, I got a another interrupt. If I stopped the timer
> > interrupts stopped coming (Status was still set to 1).
> >
> >   From this behavior I assume, that every time the Timer is incremented
> > (and Timer value is past the compare value) an EDGE interrupt (that
> > means actual X->0->1 transition) is asserted. This is really interesting
> > from HW point of view. This would mean, that a9_gtimer_update function
> > should generate the pulse and not level on compare event.
>
> That's interesting. Which version of the Cortex-A9 does this
> board have? The TRM documents that the comparator behaviour
> changed in r2p0...
>
> thanks
> -- PMM

It is "SABRE Lite (i.MX6)" board with Cortex-A9 r2p10.
Behavior is also the same for "Xilinx Zynq-7000 SoC ZC702 Evaluation 
Kit" with Cortex-A9 r3p0.

Unfortunately I do not have any board with older revision of Cortex-A9.

Best Regards,
Ing. Václav Vanc
Project Engineer

SYSGO s.r.o.
Embedding Innovations
Research and Development Center Prague
Zeleny pruh 1560/99 I CZ-14000 Praha 4
Phone: +420 222138 828, +49 6136 9948 828
Fax: +420 244911174
E-mail: vaclav.vanc@sysgo.com
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