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Re: [PATCH v7 17/42] target/arm: Restrict the values of DCZID.BS under T
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From: |
Peter Maydell |
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Subject: |
Re: [PATCH v7 17/42] target/arm: Restrict the values of DCZID.BS under TCG |
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Date: |
Thu, 18 Jun 2020 15:07:29 +0100 |
On Wed, 3 Jun 2020 at 02:13, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We can simplify our DC_ZVA if we recognize that the largest BS
> that we actually use in system mode is 64. Let us just assert
> that it fits within TARGET_PAGE_SIZE.
>
> For DC_GVA and STZGM, we want to be able to write whole bytes
> of tag memory, so assert that BS is >= 2 * TAG_GRANULE, or 32.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- Re: [PATCH v7 13/42] target/arm: Define arm_cpu_do_unaligned_access for user-only, (continued)
- [PATCH v7 12/42] target/arm: Implement the SUBP instruction, Richard Henderson, 2020/06/02
- [PATCH v7 14/42] target/arm: Add helper_probe_access, Richard Henderson, 2020/06/02
- [PATCH v7 16/42] target/arm: Implement the STGP instruction, Richard Henderson, 2020/06/02
- [PATCH v7 15/42] target/arm: Implement LDG, STG, ST2G instructions, Richard Henderson, 2020/06/02
- [PATCH v7 17/42] target/arm: Restrict the values of DCZID.BS under TCG, Richard Henderson, 2020/06/02
- Re: [PATCH v7 17/42] target/arm: Restrict the values of DCZID.BS under TCG,
Peter Maydell <=
- [PATCH v7 21/42] target/arm: Move regime_el to internals.h, Richard Henderson, 2020/06/02
- [PATCH v7 20/42] target/arm: Implement the access tag cache flushes, Richard Henderson, 2020/06/02
- [PATCH v7 18/42] target/arm: Simplify DC_ZVA, Richard Henderson, 2020/06/02
- [PATCH v7 19/42] target/arm: Implement the LDGM, STGM, STZGM instructions, Richard Henderson, 2020/06/02
- [PATCH v7 23/42] target/arm: Add gen_mte_check1, Richard Henderson, 2020/06/02