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Re: [PATCH v7 02/42] target/arm: Improve masking of SCR RES0 bits
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From: |
Peter Maydell |
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Subject: |
Re: [PATCH v7 02/42] target/arm: Improve masking of SCR RES0 bits |
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Date: |
Thu, 18 Jun 2020 11:50:18 +0100 |
On Wed, 3 Jun 2020 at 02:13, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Protect reads of aa64 id registers with ARM_CP_STATE_AA64.
> Use this as a simpler test than arm_el_is_aa64, since EL3
> cannot change mode.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- [PATCH v7 00/42] target/arm: Implement ARMv8.5-MemTag, system mode, Richard Henderson, 2020/06/02
- [PATCH v7 02/42] target/arm: Improve masking of SCR RES0 bits, Richard Henderson, 2020/06/02
- Re: [PATCH v7 02/42] target/arm: Improve masking of SCR RES0 bits,
Peter Maydell <=
- [PATCH v7 04/42] target/arm: Add support for MTE to HCR_EL2 and SCR_EL3, Richard Henderson, 2020/06/02
- [PATCH v7 05/42] target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT, Richard Henderson, 2020/06/02
- [PATCH v7 06/42] target/arm: Add DISAS_UPDATE_NOCHAIN, Richard Henderson, 2020/06/02
- [PATCH v7 07/42] target/arm: Add MTE system registers, Richard Henderson, 2020/06/02
- [PATCH v7 08/42] target/arm: Add MTE bits to tb_flags, Richard Henderson, 2020/06/02