Re: [PATCH v2 000/100] target/arm: Implement SVE2

[no-reply]

Patchew URL: 
20200618042644.1685561-1-richard.henderson@linaro.org/">https://patchew.org/QEMU/20200618042644.1685561-1-richard.henderson@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PATCH v2 000/100] target/arm: Implement SVE2
Type: series
Message-id: 20200618042644.1685561-1-richard.henderson@linaro.org

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20200615201757.16868-1-aperamak@pp1.inet.fi -> 
patchew/20200615201757.16868-1-aperamak@pp1.inet.fi
 * [new tag]         
patchew/20200618042644.1685561-1-richard.henderson@linaro.org -> 
patchew/20200618042644.1685561-1-richard.henderson@linaro.org
Switched to a new branch 'test'
2e724d0 target/arm: Implement SVE2 fp multiply-add long
1a69193 target/arm: Implement SVE2 bitwise shift immediate
b59d6c5 target/arm: Implement 128-bit ZIP, UZP, TRN
e1dfe3b target/arm: Implement SVE2 LD1RO
68bee80 target/arm: Share table of sve load functions
f10622f tcg: Implement 256-bit dup for tcg_gen_gvec_dup_mem
e59188f target/arm: Implement SVE2 FLOGB
361296a softfloat: Add float16_is_normal
9096b1b target/arm: Implement SVE2 FCVTXNT, FCVTX
93b0698 target/arm: Implement SVE2 FCVTLT
72737be target/arm: Implement SVE2 FCVTNT
1864b9a target/arm: Implement SVE2 TBL, TBX
d115f1c target/arm: Implement SVE2 crypto constructive binary operations
083365c target/arm: Implement SVE2 crypto destructive binary operations
8f530d8 target/arm: Implement SVE2 crypto unary operations
de3f6f9 target/arm: Implement SVE mixed sign dot product
9ba387a target/arm: Implement SVE mixed sign dot product (indexed)
eb4c273 target/arm: Implement SVE2 complex integer multiply-add (indexed)
beb1f42 target/arm: Implement SVE2 multiply-add long (indexed)
341d92e target/arm: Implement SVE2 saturating multiply high (indexed)
c7bf238 target/arm: Use helper_neon_sq{, r}dmul_* for aa64 advsimd
9b878ec target/arm: Implement SVE2 signed saturating doubling multiply high
734d63d target/arm: Implement SVE2 saturating multiply (indexed)
acdd6dd target/arm: Implement SVE2 integer multiply long (indexed)
2c45834 target/arm: Implement SVE2 saturating multiply-add (indexed)
3e13e5d target/arm: Implement SVE2 saturating multiply-add high (indexed)
44d1a6c target/arm: Use helper_gvec_ml{a, s}_idx_* for aa64 advsimd
958b462 target/arm: Implement SVE2 integer multiply-add (indexed)
7ec62cb target/arm: Use helper_gvec_mul_idx_* for aa64 advsimd
f545153 target/arm: Implement SVE2 integer multiply (indexed)
254440f target/arm: Split out formats for 3 vectors + 1 index
61ec4e7 target/arm: Split out formats for 2 vectors + 1 index
86dfbf2 target/arm: Pass separate addend to FCMLA helpers
9808f01 target/arm: Pass separate addend to {U, S}DOT helpers
889fb4f target/arm: Fix sve_punpk_p vs odd vector lengths
0cadee1 target/arm: Fix sve_zip_p vs odd vector lengths
c862133 target/arm: Fix sve_uzp_p vs odd vector lengths
30b5a7e target/arm: Implement SVE2 SPLICE, EXT
ca2ba7d target/arm: Implement SVE2 FMMLA
6a2a30a target/arm: Implement SVE2 gather load insns
46b60a4 target/arm: Implement SVE2 scatter store insns
f7879c3 target/arm: Implement SVE2 XAR
e6de649 target/arm: Implement SVE2 HISTCNT, HISTSEG
12f07a3 target/arm: Implement SVE2 RSUBHNB, RSUBHNT
42be129 target/arm: Implement SVE2 SUBHNB, SUBHNT
ca448c1 target/arm: Implement SVE2 RADDHNB, RADDHNT
9f13b4a target/arm: Implement SVE2 ADDHNB, ADDHNT
81f6bd0 target/arm: Implement SVE2 complex integer multiply-add
2db782a target/arm: Implement SVE2 integer multiply-add long
5ff35ee target/arm: Implement SVE2 saturating multiply-add high
7b01deb target/arm: Generalize inl_qrdmlah_* helper functions
56fe27c target/arm: Implement SVE2 saturating multiply-add long
bfc3b4a target/arm: Implement SVE2 MATCH, NMATCH
2f44fd9 target/arm: Implement SVE2 bitwise ternary operations
53ae038 target/arm: Implement SVE2 WHILERW, WHILEWR
af2cda9 target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS
b5976bb target/arm: Implement SVE2 SQSHRN, SQRSHRN
69a6d78 target/arm: Implement SVE2 UQSHRN, UQRSHRN
dca2699 target/arm: Implement SVE2 SQSHRUN, SQRSHRUN
7ac87e5 target/arm: Implement SVE2 SHRN, RSHRN
2b2f5aa target/arm: Implement SVE2 floating-point pairwise
c3a5eb0 target/arm: Implement SVE2 saturating extract narrow
2bd0506 target/arm: Implement SVE2 integer absolute difference and accumulate
5aca0f8 target/arm: Implement SVE2 bitwise shift and insert
a672202 target/arm: Implement SVE2 bitwise shift right and accumulate
8eded2d target/arm: Implement SVE2 integer add/subtract long with carry
07ef8da target/arm: Implement SVE2 integer absolute difference and accumulate 
long
3ffc1f3 target/arm: Implement SVE2 complex integer add
6659680 target/arm: Implement SVE2 bitwise permute
d144214 target/arm: Implement SVE2 bitwise exclusive-or interleaved
9398341 target/arm: Implement SVE2 bitwise shift left long
0e6d3a8 target/arm: Tidy SVE tszimm shift formats
da87e7f target/arm: Implement PMULLB and PMULLT
acd412c target/arm: Implement SVE2 integer multiply long
60b4b96 target/arm: Implement SVE2 integer add/subtract wide
23e7e0d target/arm: Implement SVE2 integer add/subtract interleaved long
9d7c56f target/arm: Implement SVE2 integer add/subtract long
b62e523 target/arm: Implement SVE2 saturating add/subtract (predicated)
44fbed6 target/arm: Implement SVE2 integer pairwise arithmetic
18f76a0 target/arm: Implement SVE2 integer halving add/subtract (predicated)
23014ad target/arm: Implement SVE2 saturating/rounding bitwise shift left 
(predicated)
94a6ee7 target/arm: Split out saturating/rounding shifts from neon
767fd07 target/arm: Implement SVE2 integer unary operations (predicated)
cb59800 target/arm: Implement SVE2 integer pairwise add and accumulate long
4a0d557 target/arm: Implement SVE2 Integer Multiply - Unpredicated
86521b4 target/arm: Enable SVE2 and some extensions
c62d6dd target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2
b59cc05 target/arm: Split out gen_gvec_ool_zz
f82a22d target/arm: Split out gen_gvec_ool_zzz
2300ff9 target/arm: Split out gen_gvec_ool_zzp
b6cb01e target/arm: Merge helper_sve_clr_* and helper_sve_movz_*
9bcbb59 target/arm: Split out gen_gvec_ool_zzzp
7e0eae3 target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp
f669e41 target/arm: Clean up 4-operand predicate expansion
26eaeb6 target/arm: Merge do_vector2_p into do_mov_p
db21129 target/arm: Rearrange {sve, fp}_check_access assert
a667857 target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn
e837aac target/arm: Split out gen_gvec_fn_zz
a0451fc qemu/int128: Add int128_lshift
92ab578 tcg: Save/restore vecop_list around minmax fallback

=== OUTPUT BEGIN ===
1/100 Checking commit 92ab578739d4 (tcg: Save/restore vecop_list around minmax 
fallback)
2/100 Checking commit a0451fcb82e4 (qemu/int128: Add int128_lshift)
3/100 Checking commit e837aac2be07 (target/arm: Split out gen_gvec_fn_zz)
4/100 Checking commit a6678572553f (target/arm: Split out gen_gvec_fn_zzz, 
do_zzz_fn)
5/100 Checking commit db211292ab26 (target/arm: Rearrange {sve, 
fp}_check_access assert)
6/100 Checking commit 26eaeb6e1352 (target/arm: Merge do_vector2_p into 
do_mov_p)
7/100 Checking commit f669e41761bf (target/arm: Clean up 4-operand predicate 
expansion)
8/100 Checking commit 7e0eae32930f (target/arm: Use tcg_gen_gvec_bitsel for 
trans_SEL_pppp)
9/100 Checking commit 9bcbb596ea8e (target/arm: Split out gen_gvec_ool_zzzp)
10/100 Checking commit b6cb01ee88d3 (target/arm: Merge helper_sve_clr_* and 
helper_sve_movz_*)
11/100 Checking commit 2300ff93d03c (target/arm: Split out gen_gvec_ool_zzp)
12/100 Checking commit f82a22dfac22 (target/arm: Split out gen_gvec_ool_zzz)
13/100 Checking commit b59cc05a0ed4 (target/arm: Split out gen_gvec_ool_zz)
14/100 Checking commit c62d6dd9d401 (target/arm: Add ID_AA64ZFR0 fields and 
isar_feature_aa64_sve2)
15/100 Checking commit 86521b465c66 (target/arm: Enable SVE2 and some 
extensions)
16/100 Checking commit 4a0d557fbb73 (target/arm: Implement SVE2 Integer 
Multiply - Unpredicated)
17/100 Checking commit cb59800c5ed2 (target/arm: Implement SVE2 integer 
pairwise add and accumulate long)
18/100 Checking commit 767fd07bbdde (target/arm: Implement SVE2 integer unary 
operations (predicated))
19/100 Checking commit 94a6ee7f8089 (target/arm: Split out saturating/rounding 
shifts from neon)
20/100 Checking commit 23014ad222b5 (target/arm: Implement SVE2 
saturating/rounding bitwise shift left (predicated))
21/100 Checking commit 18f76a011839 (target/arm: Implement SVE2 integer halving 
add/subtract (predicated))
22/100 Checking commit 44fbed6f6b19 (target/arm: Implement SVE2 integer 
pairwise arithmetic)
23/100 Checking commit b62e5235898f (target/arm: Implement SVE2 saturating 
add/subtract (predicated))
24/100 Checking commit 9d7c56f55b0e (target/arm: Implement SVE2 integer 
add/subtract long)
25/100 Checking commit 23e7e0d2433d (target/arm: Implement SVE2 integer 
add/subtract interleaved long)
26/100 Checking commit 60b4b96e298a (target/arm: Implement SVE2 integer 
add/subtract wide)
27/100 Checking commit acd412cc3b42 (target/arm: Implement SVE2 integer 
multiply long)
28/100 Checking commit da87e7f7d7d8 (target/arm: Implement PMULLB and PMULLT)
29/100 Checking commit 0e6d3a8a1517 (target/arm: Tidy SVE tszimm shift formats)
30/100 Checking commit 93983410ec3b (target/arm: Implement SVE2 bitwise shift 
left long)
ERROR: trailing whitespace
#192: FILE: target/arm/translate-sve.c:5731:
+    static const TCGOpcode sshll_list[] = { $

ERROR: trailing whitespace
#195: FILE: target/arm/translate-sve.c:5734:
+    static const TCGOpcode ushll_list[] = { $

ERROR: trailing whitespace
#199: FILE: target/arm/translate-sve.c:5738:
+        { { .fniv = gen_sshll_vec, $

ERROR: trailing whitespace
#203: FILE: target/arm/translate-sve.c:5742:
+          { .fniv = gen_sshll_vec, $

ERROR: trailing whitespace
#207: FILE: target/arm/translate-sve.c:5746:
+          { .fniv = gen_sshll_vec, $

total: 5 errors, 0 warnings, 228 lines checked

Patch 30/100 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

31/100 Checking commit d144214a60b4 (target/arm: Implement SVE2 bitwise 
exclusive-or interleaved)
32/100 Checking commit 66596804a18f (target/arm: Implement SVE2 bitwise permute)
33/100 Checking commit 3ffc1f39714c (target/arm: Implement SVE2 complex integer 
add)
34/100 Checking commit 07ef8daf3496 (target/arm: Implement SVE2 integer 
absolute difference and accumulate long)
35/100 Checking commit 8eded2d28776 (target/arm: Implement SVE2 integer 
add/subtract long with carry)
36/100 Checking commit a6722020023a (target/arm: Implement SVE2 bitwise shift 
right and accumulate)
37/100 Checking commit 5aca0f87b943 (target/arm: Implement SVE2 bitwise shift 
and insert)
38/100 Checking commit 2bd0506ac693 (target/arm: Implement SVE2 integer 
absolute difference and accumulate)
39/100 Checking commit c3a5eb0c0af6 (target/arm: Implement SVE2 saturating 
extract narrow)
40/100 Checking commit 2b2f5aacd729 (target/arm: Implement SVE2 floating-point 
pairwise)
41/100 Checking commit 7ac87e5507e0 (target/arm: Implement SVE2 SHRN, RSHRN)
42/100 Checking commit dca2699f5514 (target/arm: Implement SVE2 SQSHRUN, 
SQRSHRUN)
43/100 Checking commit 69a6d7813e6b (target/arm: Implement SVE2 UQSHRN, UQRSHRN)
44/100 Checking commit b5976bb05c96 (target/arm: Implement SVE2 SQSHRN, SQRSHRN)
45/100 Checking commit af2cda94a3b2 (target/arm: Implement SVE2 WHILEGT, 
WHILEGE, WHILEHI, WHILEHS)
46/100 Checking commit 53ae038cdd8d (target/arm: Implement SVE2 WHILERW, 
WHILEWR)
47/100 Checking commit 2f44fd901c0b (target/arm: Implement SVE2 bitwise ternary 
operations)
48/100 Checking commit bfc3b4a6eb08 (target/arm: Implement SVE2 MATCH, NMATCH)
49/100 Checking commit 56fe27ce330e (target/arm: Implement SVE2 saturating 
multiply-add long)
50/100 Checking commit 7b01deb0bbbd (target/arm: Generalize inl_qrdmlah_* 
helper functions)
51/100 Checking commit 5ff35ee05906 (target/arm: Implement SVE2 saturating 
multiply-add high)
52/100 Checking commit 2db782af4a7e (target/arm: Implement SVE2 integer 
multiply-add long)
53/100 Checking commit 81f6bd0e77ee (target/arm: Implement SVE2 complex integer 
multiply-add)
54/100 Checking commit 9f13b4a361f7 (target/arm: Implement SVE2 ADDHNB, ADDHNT)
55/100 Checking commit ca448c18b058 (target/arm: Implement SVE2 RADDHNB, 
RADDHNT)
56/100 Checking commit 42be129f4d88 (target/arm: Implement SVE2 SUBHNB, SUBHNT)
57/100 Checking commit 12f07a3c40b3 (target/arm: Implement SVE2 RSUBHNB, 
RSUBHNT)
58/100 Checking commit e6de649948fa (target/arm: Implement SVE2 HISTCNT, 
HISTSEG)
WARNING: Block comments use a trailing */ on a separate line
#135: FILE: target/arm/sve_helper.c:6736:
+ * */

total: 0 errors, 1 warnings, 183 lines checked

Patch 58/100 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
59/100 Checking commit f7879c328b69 (target/arm: Implement SVE2 XAR)
60/100 Checking commit 46b60a4f98ef (target/arm: Implement SVE2 scatter store 
insns)
61/100 Checking commit 6a2a30add7c1 (target/arm: Implement SVE2 gather load 
insns)
62/100 Checking commit ca2ba7dab817 (target/arm: Implement SVE2 FMMLA)
63/100 Checking commit 30b5a7e17138 (target/arm: Implement SVE2 SPLICE, EXT)
64/100 Checking commit c8621330902e (target/arm: Fix sve_uzp_p vs odd vector 
lengths)
65/100 Checking commit 0cadee1c09b6 (target/arm: Fix sve_zip_p vs odd vector 
lengths)
66/100 Checking commit 889fb4f1f5d1 (target/arm: Fix sve_punpk_p vs odd vector 
lengths)
67/100 Checking commit 9808f013d719 (target/arm: Pass separate addend to {U, 
S}DOT helpers)
68/100 Checking commit 86dfbf2310ee (target/arm: Pass separate addend to FCMLA 
helpers)
WARNING: Block comments use a leading /* on a separate line
#53: FILE: target/arm/translate-a64.c:619:
+/* Expand a 4-operand + fpstatus pointer + simd data value operation using

total: 0 errors, 1 warnings, 254 lines checked

Patch 68/100 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
69/100 Checking commit 61ec4e7255cd (target/arm: Split out formats for 2 
vectors + 1 index)
70/100 Checking commit 254440f28248 (target/arm: Split out formats for 3 
vectors + 1 index)
71/100 Checking commit f545153e0c3b (target/arm: Implement SVE2 integer 
multiply (indexed))
ERROR: space prohibited before that close parenthesis ')'
#121: FILE: target/arm/vec_helper.c:882:
+DO_MUL_IDX(gvec_mul_idx_d, uint64_t, )

ERROR: space prohibited before that close parenthesis ')'
#138: FILE: target/arm/vec_helper.c:903:
+DO_FMUL_IDX(gvec_fmul_idx_d, float64, )

total: 2 errors, 0 warnings, 113 lines checked

Patch 71/100 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

72/100 Checking commit 7ec62cbdd62d (target/arm: Use helper_gvec_mul_idx_* for 
aa64 advsimd)
73/100 Checking commit 958b4624c3a7 (target/arm: Implement SVE2 integer 
multiply-add (indexed))
ERROR: space prohibited before that close parenthesis ')'
#113: FILE: target/arm/vec_helper.c:903:
+DO_MLA_IDX(gvec_mla_idx_d, uint64_t, +,   )

ERROR: space prohibited before that close parenthesis ')'
#117: FILE: target/arm/vec_helper.c:907:
+DO_MLA_IDX(gvec_mls_idx_d, uint64_t, -,   )

total: 2 errors, 0 warnings, 94 lines checked

Patch 73/100 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

74/100 Checking commit 44d1a6c45264 (target/arm: Use helper_gvec_ml{a, s}_idx_* 
for aa64 advsimd)
75/100 Checking commit 3e13e5d7705d (target/arm: Implement SVE2 saturating 
multiply-add high (indexed))
76/100 Checking commit 2c45834f39b8 (target/arm: Implement SVE2 saturating 
multiply-add (indexed))
77/100 Checking commit acdd6dd65da1 (target/arm: Implement SVE2 integer 
multiply long (indexed))
78/100 Checking commit 734d63d8afd9 (target/arm: Implement SVE2 saturating 
multiply (indexed))
79/100 Checking commit 9b878ece5be3 (target/arm: Implement SVE2 signed 
saturating doubling multiply high)
80/100 Checking commit c7bf2383bba8 (target/arm: Use helper_neon_sq{, r}dmul_* 
for aa64 advsimd)
81/100 Checking commit 341d92e3c94e (target/arm: Implement SVE2 saturating 
multiply high (indexed))
82/100 Checking commit beb1f425a064 (target/arm: Implement SVE2 multiply-add 
long (indexed))
83/100 Checking commit eb4c27354d53 (target/arm: Implement SVE2 complex integer 
multiply-add (indexed))
ERROR: spaces required around that '*' (ctx:WxV)
#281: FILE: target/arm/translate-sve.c:3973:
+static bool trans_##NAME(DisasContext *s, arg_##NAME *a)       \
                                                      ^

total: 1 errors, 0 warnings, 265 lines checked

Patch 83/100 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

84/100 Checking commit 9ba387a03a78 (target/arm: Implement SVE mixed sign dot 
product (indexed))
WARNING: Block comments use a leading /* on a separate line
#102: FILE: target/arm/vec_helper.c:690:
+    /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd.

WARNING: Block comments use a leading /* on a separate line
#135: FILE: target/arm/vec_helper.c:723:
+    /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd.

total: 0 errors, 2 warnings, 127 lines checked

Patch 84/100 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
85/100 Checking commit de3f6f979e31 (target/arm: Implement SVE mixed sign dot 
product)
86/100 Checking commit 8f530d844734 (target/arm: Implement SVE2 crypto unary 
operations)
87/100 Checking commit 083365c8e742 (target/arm: Implement SVE2 crypto 
destructive binary operations)
88/100 Checking commit d115f1c59453 (target/arm: Implement SVE2 crypto 
constructive binary operations)
89/100 Checking commit 1864b9ac6599 (target/arm: Implement SVE2 TBL, TBX)
ERROR: space prohibited before that close parenthesis ')'
#148: FILE: target/arm/sve_helper.c:3088:
+DO_TB(d, uint64_t,   )

total: 1 errors, 0 warnings, 165 lines checked

Patch 89/100 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

90/100 Checking commit 72737be7aa94 (target/arm: Implement SVE2 FCVTNT)
91/100 Checking commit 93b06980556f (target/arm: Implement SVE2 FCVTLT)
92/100 Checking commit 9096b1b8c693 (target/arm: Implement SVE2 FCVTXNT, FCVTX)
93/100 Checking commit 361296af82a2 (softfloat: Add float16_is_normal)
94/100 Checking commit e59188f34932 (target/arm: Implement SVE2 FLOGB)
95/100 Checking commit f10622f49581 (tcg: Implement 256-bit dup for 
tcg_gen_gvec_dup_mem)
96/100 Checking commit 68bee80d1304 (target/arm: Share table of sve load 
functions)
97/100 Checking commit e1dfe3bc4032 (target/arm: Implement SVE2 LD1RO)
98/100 Checking commit b59d6c5b79a0 (target/arm: Implement 128-bit ZIP, UZP, 
TRN)
ERROR: space prohibited before that close parenthesis ')'
#70: FILE: target/arm/sve_helper.c:3498:
+DO_ZIP(sve2_zip_q, Int128, )

ERROR: space prohibited before that close parenthesis ')'
#107: FILE: target/arm/sve_helper.c:3527:
+DO_UZP(sve2_uzp_q, Int128, )

ERROR: space prohibited before that close parenthesis ')'
#124: FILE: target/arm/sve_helper.c:3550:
+DO_TRN(sve2_trn_q, Int128, )

total: 3 errors, 0 warnings, 178 lines checked

Patch 98/100 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

99/100 Checking commit 1a69193cc8c9 (target/arm: Implement SVE2 bitwise shift 
immediate)
100/100 Checking commit 2e724d00d03b (target/arm: Implement SVE2 fp 
multiply-add long)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
20200618042644.1685561-1-richard.henderson@linaro.org/testing.checkpatch/?type=message">http://patchew.org/logs/20200618042644.1685561-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
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