[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 064/100] target/arm: Fix sve_uzp_p vs odd vector lengths
From: |
Richard Henderson |
Subject: |
[PATCH v2 064/100] target/arm: Fix sve_uzp_p vs odd vector lengths |
Date: |
Wed, 17 Jun 2020 21:26:08 -0700 |
Missed out on compressing the second half of a predicate
with length vl % 512 > 256.
Adjust all of the x + (y << s) to x | (y << s) as a
general style fix.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sve_helper.c | 30 +++++++++++++++++++++---------
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index b1bb2300f8..f0601bf25b 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -2971,7 +2971,7 @@ void HELPER(sve_uzp_p)(void *vd, void *vn, void *vm,
uint32_t pred_desc)
if (oprsz <= 8) {
l = compress_bits(n[0] >> odd, esz);
h = compress_bits(m[0] >> odd, esz);
- d[0] = extract64(l + (h << (4 * oprsz)), 0, 8 * oprsz);
+ d[0] = l | (h << (4 * oprsz));
} else {
ARMPredicateReg tmp_m;
intptr_t oprsz_16 = oprsz / 16;
@@ -2985,23 +2985,35 @@ void HELPER(sve_uzp_p)(void *vd, void *vn, void *vm,
uint32_t pred_desc)
h = n[2 * i + 1];
l = compress_bits(l >> odd, esz);
h = compress_bits(h >> odd, esz);
- d[i] = l + (h << 32);
+ d[i] = l | (h << 32);
}
- /* For VL which is not a power of 2, the results from M do not
- align nicely with the uint64_t for D. Put the aligned results
- from M into TMP_M and then copy it into place afterward. */
+ /*
+ * For VL which is not a multiple of 512, the results from M do not
+ * align nicely with the uint64_t for D. Put the aligned results
+ * from M into TMP_M and then copy it into place afterward.
+ */
if (oprsz & 15) {
- d[i] = compress_bits(n[2 * i] >> odd, esz);
+ int final_shift = (oprsz & 15) * 2;
+
+ l = n[2 * i + 0];
+ h = n[2 * i + 1];
+ l = compress_bits(l >> odd, esz);
+ h = compress_bits(h >> odd, esz);
+ d[i] = l | (h << final_shift);
for (i = 0; i < oprsz_16; i++) {
l = m[2 * i + 0];
h = m[2 * i + 1];
l = compress_bits(l >> odd, esz);
h = compress_bits(h >> odd, esz);
- tmp_m.p[i] = l + (h << 32);
+ tmp_m.p[i] = l | (h << 32);
}
- tmp_m.p[i] = compress_bits(m[2 * i] >> odd, esz);
+ l = m[2 * i + 0];
+ h = m[2 * i + 1];
+ l = compress_bits(l >> odd, esz);
+ h = compress_bits(h >> odd, esz);
+ tmp_m.p[i] = l | (h << final_shift);
swap_memmove(vd + oprsz / 2, &tmp_m, oprsz / 2);
} else {
@@ -3010,7 +3022,7 @@ void HELPER(sve_uzp_p)(void *vd, void *vn, void *vm,
uint32_t pred_desc)
h = m[2 * i + 1];
l = compress_bits(l >> odd, esz);
h = compress_bits(h >> odd, esz);
- d[oprsz_16 + i] = l + (h << 32);
+ d[oprsz_16 + i] = l | (h << 32);
}
}
}
--
2.25.1
- [PATCH v2 055/100] target/arm: Implement SVE2 RADDHNB, RADDHNT, (continued)
- [PATCH v2 055/100] target/arm: Implement SVE2 RADDHNB, RADDHNT, Richard Henderson, 2020/06/18
- [PATCH v2 056/100] target/arm: Implement SVE2 SUBHNB, SUBHNT, Richard Henderson, 2020/06/18
- [PATCH v2 053/100] target/arm: Implement SVE2 complex integer multiply-add, Richard Henderson, 2020/06/18
- [PATCH v2 054/100] target/arm: Implement SVE2 ADDHNB, ADDHNT, Richard Henderson, 2020/06/18
- [PATCH v2 057/100] target/arm: Implement SVE2 RSUBHNB, RSUBHNT, Richard Henderson, 2020/06/18
- [PATCH v2 058/100] target/arm: Implement SVE2 HISTCNT, HISTSEG, Richard Henderson, 2020/06/18
- [PATCH v2 059/100] target/arm: Implement SVE2 XAR, Richard Henderson, 2020/06/18
- [PATCH v2 060/100] target/arm: Implement SVE2 scatter store insns, Richard Henderson, 2020/06/18
- [PATCH v2 063/100] target/arm: Implement SVE2 SPLICE, EXT, Richard Henderson, 2020/06/18
- [PATCH v2 062/100] target/arm: Implement SVE2 FMMLA, Richard Henderson, 2020/06/18
- [PATCH v2 064/100] target/arm: Fix sve_uzp_p vs odd vector lengths,
Richard Henderson <=
- [PATCH v2 061/100] target/arm: Implement SVE2 gather load insns, Richard Henderson, 2020/06/18
- [PATCH v2 065/100] target/arm: Fix sve_zip_p vs odd vector lengths, Richard Henderson, 2020/06/18
- [PATCH v2 066/100] target/arm: Fix sve_punpk_p vs odd vector lengths, Richard Henderson, 2020/06/18
- [PATCH v2 067/100] target/arm: Pass separate addend to {U, S}DOT helpers, Richard Henderson, 2020/06/18
- [PATCH v2 069/100] target/arm: Split out formats for 2 vectors + 1 index, Richard Henderson, 2020/06/18
- [PATCH v2 068/100] target/arm: Pass separate addend to FCMLA helpers, Richard Henderson, 2020/06/18
- [PATCH v2 070/100] target/arm: Split out formats for 3 vectors + 1 index, Richard Henderson, 2020/06/18
- [PATCH v2 071/100] target/arm: Implement SVE2 integer multiply (indexed), Richard Henderson, 2020/06/18
- [PATCH v2 072/100] target/arm: Use helper_gvec_mul_idx_* for aa64 advsimd, Richard Henderson, 2020/06/18
- [PATCH v2 075/100] target/arm: Implement SVE2 saturating multiply-add high (indexed), Richard Henderson, 2020/06/18