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[PATCH v2 008/100] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_ppp
From: |
Richard Henderson |
Subject: |
[PATCH v2 008/100] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp |
Date: |
Wed, 17 Jun 2020 21:25:12 -0700 |
The gvec operation was added after the initial implementation
of the SEL instruction and was missed in the conversion.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-sve.c | 31 ++++++++-----------------------
1 file changed, 8 insertions(+), 23 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 6d1a69c365..741f4d8b32 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -1188,34 +1188,19 @@ static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s
*a)
return do_pppp_flags(s, a, &op);
}
-static void gen_sel_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
-{
- tcg_gen_and_i64(pn, pn, pg);
- tcg_gen_andc_i64(pm, pm, pg);
- tcg_gen_or_i64(pd, pn, pm);
-}
-
-static void gen_sel_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn,
- TCGv_vec pm, TCGv_vec pg)
-{
- tcg_gen_and_vec(vece, pn, pn, pg);
- tcg_gen_andc_vec(vece, pm, pm, pg);
- tcg_gen_or_vec(vece, pd, pn, pm);
-}
-
static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a)
{
- static const GVecGen4 op = {
- .fni8 = gen_sel_pg_i64,
- .fniv = gen_sel_pg_vec,
- .fno = gen_helper_sve_sel_pppp,
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
- };
-
if (a->s) {
return false;
}
- return do_pppp_flags(s, a, &op);
+ if (sve_access_check(s)) {
+ unsigned psz = pred_gvec_reg_size(s);
+ tcg_gen_gvec_bitsel(MO_8, pred_full_reg_offset(s, a->rd),
+ pred_full_reg_offset(s, a->pg),
+ pred_full_reg_offset(s, a->rn),
+ pred_full_reg_offset(s, a->rm), psz, psz);
+ }
+ return true;
}
static void gen_orr_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
--
2.25.1
- [PATCH v2 000/100] target/arm: Implement SVE2, Richard Henderson, 2020/06/18
- [PATCH v2 001/100] tcg: Save/restore vecop_list around minmax fallback, Richard Henderson, 2020/06/18
- [PATCH v2 003/100] target/arm: Split out gen_gvec_fn_zz, Richard Henderson, 2020/06/18
- [PATCH v2 002/100] qemu/int128: Add int128_lshift, Richard Henderson, 2020/06/18
- [PATCH v2 004/100] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn, Richard Henderson, 2020/06/18
- [PATCH v2 005/100] target/arm: Rearrange {sve, fp}_check_access assert, Richard Henderson, 2020/06/18
- [PATCH v2 006/100] target/arm: Merge do_vector2_p into do_mov_p, Richard Henderson, 2020/06/18
- [PATCH v2 007/100] target/arm: Clean up 4-operand predicate expansion, Richard Henderson, 2020/06/18
- [PATCH v2 008/100] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp,
Richard Henderson <=
- [PATCH v2 009/100] target/arm: Split out gen_gvec_ool_zzzp, Richard Henderson, 2020/06/18
- [PATCH v2 011/100] target/arm: Split out gen_gvec_ool_zzp, Richard Henderson, 2020/06/18
- [PATCH v2 012/100] target/arm: Split out gen_gvec_ool_zzz, Richard Henderson, 2020/06/18
- [PATCH v2 010/100] target/arm: Merge helper_sve_clr_* and helper_sve_movz_*, Richard Henderson, 2020/06/18
- [PATCH v2 013/100] target/arm: Split out gen_gvec_ool_zz, Richard Henderson, 2020/06/18
- [PATCH v2 014/100] target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2, Richard Henderson, 2020/06/18
- [PATCH v2 016/100] target/arm: Implement SVE2 Integer Multiply - Unpredicated, Richard Henderson, 2020/06/18
- [PATCH v2 015/100] target/arm: Enable SVE2 and some extensions, Richard Henderson, 2020/06/18
- [PATCH v2 018/100] target/arm: Implement SVE2 integer unary operations (predicated), Richard Henderson, 2020/06/18
- [PATCH v2 017/100] target/arm: Implement SVE2 integer pairwise add and accumulate long, Richard Henderson, 2020/06/18