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Re: [PATCH] docs/system: Document Aspeed boards
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From: |
Andrew Jeffery |
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Subject: |
Re: [PATCH] docs/system: Document Aspeed boards |
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Date: |
Wed, 03 Jun 2020 10:15:59 +0930 |
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User-agent: |
Cyrus-JMAP/3.3.0-dev0-519-g0f677ba-fm-20200601.001-g0f677ba6 |
>
> >> + * Hash/Crypto Engine
> >> + * PCI-Express 1 Controller
> >> + * Graphic Display Controller
> >> + * PECI Controller
> >> + * MCTP Controller
> >> + * Mailbox Controller
> >> + * Virtual UART
> >
> > Uh what is that? :)
>
> It is the host console.
>
To explain a little more, a 16550-compatible set of registers are exposed to
both the host (via e.g. the LPC bus) and the BMC, but the FIFOs are shared and
the transmissions are nothing more than register writes/reads from each side.
There's no RS-232 involved, hence "Virtual" I guess.
Andrew