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[PATCH 1/8] hw/arm/aspeed: Correct DRAM container region size
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 1/8] hw/arm/aspeed: Correct DRAM container region size |
Date: |
Sun, 31 May 2020 19:38:07 +0200 |
memory_region_set_size() handle the 16 Exabytes limit by
special-casing the UINT64_MAX value. This is not a problem
for the 32-bit maximum, 4 GiB.
By using the UINT32_MAX value, the aspeed-ram-container
MemoryRegion ends up missing 1 byte:
$ qemu-system-arm -M ast2600-evb -S -monitor stdio
(qemu) info mtree
address-space: aspeed.fmc-ast2600-dma-dram
0000000080000000-000000017ffffffe (prio 0, i/o): aspeed-ram-container
0000000080000000-00000000bfffffff (prio 0, ram): ram
00000000c0000000-ffffffffffffffff (prio 0, i/o): max_ram
Fix by using the correct value. We now have:
address-space: aspeed.fmc-ast2600-dma-dram
0000000080000000-000000017fffffff (prio 0, i/o): aspeed-ram-container
0000000080000000-00000000bfffffff (prio 0, ram): ram
00000000c0000000-ffffffffffffffff (prio 0, i/o): max_ram
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/arm/aspeed.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 2c23297edf..62344ac6a3 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -262,7 +262,7 @@ static void aspeed_machine_init(MachineState *machine)
bmc = g_new0(AspeedBoardState, 1);
memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container",
- UINT32_MAX);
+ 4 * GiB);
memory_region_add_subregion(&bmc->ram_container, 0, machine->ram);
object_initialize_child(OBJECT(machine), "soc", &bmc->soc,
--
2.21.3
- [PATCH 0/8] hw: Fix some incomplete memory region size, Philippe Mathieu-Daudé, 2020/05/31
- [PATCH 1/8] hw/arm/aspeed: Correct DRAM container region size,
Philippe Mathieu-Daudé <=
- [PATCH 2/8] hw/pci-host/prep: Correct RAVEN bus bridge memory region size, Philippe Mathieu-Daudé, 2020/05/31
- [PATCH 5/8] hw/pci-host: Use the IEC binary prefix definitions, Philippe Mathieu-Daudé, 2020/05/31
- [PATCH 3/8] hw/pci/pci_bridge: Correct pci_bridge_io memory region size, Philippe Mathieu-Daudé, 2020/05/31
- [PATCH 8/8] target/i386/cpu: Use the IEC binary prefix definitions, Philippe Mathieu-Daudé, 2020/05/31
- [PATCH 6/8] hw/hppa/dino: Use the IEC binary prefix definitions, Philippe Mathieu-Daudé, 2020/05/31
- [PATCH 4/8] hw/pci/pci_bridge: Use the IEC binary prefix definitions, Philippe Mathieu-Daudé, 2020/05/31
- [PATCH 7/8] hw/i386/xen/xen-hvm: Use the IEC binary prefix definitions, Philippe Mathieu-Daudé, 2020/05/31
- Re: [PATCH 0/8] hw: Fix some incomplete memory region size, Peter Maydell, 2020/05/31