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[PATCH v5 11/12] net: cadence_gem: TX_LAST bit should be set by guest
From: |
Sai Pavan Boddu |
Subject: |
[PATCH v5 11/12] net: cadence_gem: TX_LAST bit should be set by guest |
Date: |
Tue, 12 May 2020 20:24:53 +0530 |
TX_LAST bit should not be set by hardware, its set by guest to inform
the last bd of the frame.
Signed-off-by: Sai Pavan Boddu <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
---
hw/net/cadence_gem.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index ddb8938..57d94a5 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -350,11 +350,6 @@ static inline unsigned tx_desc_get_last(uint32_t *desc)
return (desc[1] & DESC_1_TX_LAST) ? 1 : 0;
}
-static inline void tx_desc_set_last(uint32_t *desc)
-{
- desc[1] |= DESC_1_TX_LAST;
-}
-
static inline unsigned tx_desc_get_length(uint32_t *desc)
{
return desc[1] & DESC_1_LENGTH;
@@ -1298,7 +1293,6 @@ static void gem_transmit(CadenceGEMState *s)
/* read next descriptor */
if (tx_desc_get_wrap(desc)) {
- tx_desc_set_last(desc);
if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
packet_desc_addr = s->regs[GEM_TBQPH];
--
2.7.4
- [PATCH v5 04/12] net: cadence_gem: Define access permission for interrupt registers, (continued)
- [PATCH v5 04/12] net: cadence_gem: Define access permission for interrupt registers, Sai Pavan Boddu, 2020/05/12
- [PATCH v5 01/12] net: cadence_gem: Fix debug statements, Sai Pavan Boddu, 2020/05/12
- [PATCH v5 02/12] net: cadence_gem: Fix the queue address update during wrap around, Sai Pavan Boddu, 2020/05/12
- [PATCH v5 06/12] net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState, Sai Pavan Boddu, 2020/05/12
- [PATCH v5 12/12] net: cadence_gem: Fix RX address filtering, Sai Pavan Boddu, 2020/05/12
- [PATCH v5 07/12] net: cadence_gem: Fix up code style, Sai Pavan Boddu, 2020/05/12
- [PATCH v5 09/12] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg, Sai Pavan Boddu, 2020/05/12
- [PATCH v5 10/12] net: cadence_gem: Update the reset value for interrupt mask register, Sai Pavan Boddu, 2020/05/12
- [PATCH v5 05/12] net: cadence_gem: Set ISR according to queue in use, Sai Pavan Boddu, 2020/05/12
- [PATCH v5 11/12] net: cadence_gem: TX_LAST bit should be set by guest,
Sai Pavan Boddu <=
- [PATCH v5 08/12] net: cadence_gem: Add support for jumbo frames, Sai Pavan Boddu, 2020/05/12
- Re: [PATCH v5 00/12] Cadence GEM Fixes, Jason Wang, 2020/05/14