Re: [PATCH 31/36] target/arm: Convert Neon VADD, VSUB, VABD 3-reg-same insns to decodetree

[Richard Henderson]

On 4/30/20 11:09 AM, Peter Maydell wrote:
> +    TCGv_ptr fpstatus = get_fpstatus_ptr(1);
> +    for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
> +        tmp = neon_load_reg(a->vn, pass);
> +        tmp2 = neon_load_reg(a->vm, pass);
> +        fn(tmp, tmp, tmp2, fpstatus);
> +        tcg_temp_free_i32(tmp2);
> +        neon_store_reg(a->vd, pass, tmp);
> +    }
> +    tcg_temp_free_ptr(fpstatus);
> +    return true;
> +}
> +
> +/*
> + * For all the functions using this macro, size == 1 means fp16,
> + * which is an architecture extension we don't implement yet.
> + */
> +#define DO_3S_FP(INSN,FUNC)                                         \
> +    static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \
> +    {                                                               \
> +        if (a->size != 0) {                                         \
> +            /* TODO fp16 support */                                 \
> +            return false;                                           \
> +        }                                                           \
> +        return do_3same_fp(s, a, FUNC);                             \
> +    }

We already have helper_gvec_fadd_s and helper_fsub_s to handle the whole vector
with one call.  Use with tcg_gen_gvec_3_ptr, with the status pointer as the 4th
argument.

Interestingly, I can't find the current use of this helper.  I must have been
starting on that translation but got stopped?  There's no current full-vector
helper for abd_f32, but it would take very few lines to add it.


r~