Re: [PATCH] target/arm: Use correct variable for setting 'max' cpu's MIDR_EL1

[Peter Maydell]

On Thu, 23 Apr 2020 at 14:08, Laurent Desnogues
<address@hidden> wrote:
> On Thu, Apr 23, 2020 at 2:44 PM Philippe Mathieu-Daudé <address@hidden> wrote:
> >
> > MIDR_EL1 is a 32-bit register.
>
> In fact MIDR_EL1 a 64-bit system register with the top 32-bit being RES0.
>
> So the right fix might be to change midr field size, just to be future proof 
> :-)

Yes, I think I prefer changing the midr field size. Looking at the
code this should just be a matter of updating the 'uint32_t midr' in
the CPU struct to 'uint64_t midr' and changing the
DEFINE_PROP_UINT32("midr",...)
in cpu.c to UINT64. (The one user of the property in xlnx-zynqmp.c
doesn't need to change because object_property_set_int() works on
both 32-bit and 64-bit integer properties.)

Mostly we have been fixing up these ID register field size values as
we move them from being top-level ARMCPU fields to being in the
ARMISARegisters struct, but I think midr is unlikely to ever need
to move there because no CPU feature is gated on the MIDR value.

thanks
-- PMM