[PATCH RFC] target/arm: Implement SVE2 SPLICE, EXT

[Stephen Long]

Signed-off-by: Stephen Long <address@hidden>

I'm not sure I can just use the SVE helper functions for the SVE2
variants of EXT and SPLICE.
---
 target/arm/sve.decode      |  8 ++++++++
 target/arm/translate-sve.c | 39 +++++++++++++++++++++++++++++++++-----
 2 files changed, 42 insertions(+), 5 deletions(-)

diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 3a2a4a7f1c..004cbb4191 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1387,3 +1387,11 @@ UMLSLT_zzzw     01000100 .. 0 ..... 010 111 ..... .....  
@rda_rn_rm
 
 CMLA_zzzz       01000100 esz:2 0 rm:5 0010 rot:2 rn:5 rd:5  ra=%reg_movprfx
 SQRDCMLAH_zzzz  01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5  ra=%reg_movprfx
+
+### SVE2 vector splice (predicated, constructive)
+
+SPLICE_zpz      00000101 .. 101 101 100 ... ..... .....     @rd_pg_rn
+
+### SVE2 extract vector (immediate offset)
+EXT_zzi         00000101 011 ..... 000 ... rn:5 rd:5 \
+                    &rri imm=%imm8_16_10
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 20eb588cb3..8c34785449 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -2269,18 +2269,18 @@ static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i 
*a)
  *** SVE Permute Extract Group
  */
 
-static bool trans_EXT(DisasContext *s, arg_EXT *a)
+static bool do_EXT(DisasContext *s, int rd, int rn, int rm, int imm)
 {
     if (!sve_access_check(s)) {
         return true;
     }
 
     unsigned vsz = vec_full_reg_size(s);
-    unsigned n_ofs = a->imm >= vsz ? 0 : a->imm;
+    unsigned n_ofs = imm >= vsz ? 0 : imm;
     unsigned n_siz = vsz - n_ofs;
-    unsigned d = vec_full_reg_offset(s, a->rd);
-    unsigned n = vec_full_reg_offset(s, a->rn);
-    unsigned m = vec_full_reg_offset(s, a->rm);
+    unsigned d = vec_full_reg_offset(s, rd);
+    unsigned n = vec_full_reg_offset(s, rn);
+    unsigned m = vec_full_reg_offset(s, rm);
 
     /* Use host vector move insns if we have appropriate sizes
      * and no unfortunate overlap.
@@ -2299,6 +2299,11 @@ static bool trans_EXT(DisasContext *s, arg_EXT *a)
     return true;
 }
 
+static bool trans_EXT(DisasContext *s, arg_EXT *a)
+{
+    return do_EXT(s, a->rd, a->rn, a->rm, a->imm);
+}
+
 /*
  *** SVE Permute - Unpredicated Group
  */
@@ -7882,3 +7887,27 @@ static bool trans_SQRDCMLAH_zzzz(DisasContext *s, 
arg_CMLA_zzzz *a)
     };
     return do_sve2_zzzz_fn(s, a->rd, a->rn, a->rm, a->ra, fns[a->esz], a->rot);
 }
+
+static bool trans_SPLICE_zpz(DisasContext *s, arg_rpr_esz *a)
+{
+    if (!dc_isar_feature(aa64_sve2, s)) {
+        return false;
+    }
+    if (sve_access_check(s)) {
+        unsigned vsz = vec_full_reg_size(s);
+        tcg_gen_gvec_4_ool(vec_full_reg_offset(s, a->rd),
+                           vec_full_reg_offset(s, a->rn),
+                           vec_full_reg_offset(s, (a->rn + 1) % 32),
+                           pred_full_reg_offset(s, a->pg),
+                           vsz, vsz, a->esz, gen_helper_sve_splice);
+    }
+    return true;
+}
+
+static bool trans_EXT_zzi(DisasContext *s, arg_rri *a)
+{
+    if (!dc_isar_feature(aa64_sve2, s)) {
+        return false;
+    }
+    return do_EXT(s, a->rd, a->rn, (a->rn + 1) % 32, a->imm);
+}
-- 
2.17.1