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[PATCH 16/31] target/arm: Tidy SVE tszimm shift formats
From: |
Richard Henderson |
Subject: |
[PATCH 16/31] target/arm: Tidy SVE tszimm shift formats |
Date: |
Thu, 26 Mar 2020 16:08:23 -0700 |
Rather than require the user to fill in the immediate (shl or shr),
create full formats that include the immediate.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/sve.decode | 35 ++++++++++++++++-------------------
1 file changed, 16 insertions(+), 19 deletions(-)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 04bf9e5ce8..440cff4597 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -151,13 +151,17 @@
@rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri
# Two register operand, one immediate operand, with predicate,
-# element size encoded as TSZHL. User must fill in imm.
-@rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \
- &rpri_esz rn=%reg_movprfx esz=%tszimm_esz
+# element size encoded as TSZHL.
+@rdn_pg_tszimm_shl ........ .. ... ... ... pg:3 ..... rd:5 \
+ &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shl
+@rdn_pg_tszimm_shr ........ .. ... ... ... pg:3 ..... rd:5 \
+ &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shr
# Similarly without predicate.
-@rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \
- &rri_esz esz=%tszimm16_esz
+@rd_rn_tszimm_shl ........ .. ... ... ...... rn:5 rd:5 \
+ &rri_esz esz=%tszimm16_esz imm=%tszimm16_shl
+@rd_rn_tszimm_shr ........ .. ... ... ...... rn:5 rd:5 \
+ &rri_esz esz=%tszimm16_esz imm=%tszimm16_shr
# Two register operand, one immediate operand, with 4-bit predicate.
# User must fill in imm.
@@ -290,14 +294,10 @@ UMINV 00000100 .. 001 011 001 ... ..... .....
@rd_pg_rn
### SVE Shift by Immediate - Predicated Group
# SVE bitwise shift by immediate (predicated)
-ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \
- @rdn_pg_tszimm imm=%tszimm_shr
-LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \
- @rdn_pg_tszimm imm=%tszimm_shr
-LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \
- @rdn_pg_tszimm imm=%tszimm_shl
-ASRD 00000100 .. 000 100 100 ... .. ... ..... \
- @rdn_pg_tszimm imm=%tszimm_shr
+ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... @rdn_pg_tszimm_shr
+LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... @rdn_pg_tszimm_shr
+LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... @rdn_pg_tszimm_shl
+ASRD 00000100 .. 000 100 100 ... .. ... ..... @rdn_pg_tszimm_shr
# SVE bitwise shift by vector (predicated)
ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
@@ -401,12 +401,9 @@ RDVL 00000100 101 11111 01010 imm:s6 rd:5
### SVE Bitwise Shift - Unpredicated Group
# SVE bitwise shift by immediate (unpredicated)
-ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \
- @rd_rn_tszimm imm=%tszimm16_shr
-LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \
- @rd_rn_tszimm imm=%tszimm16_shr
-LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \
- @rd_rn_tszimm imm=%tszimm16_shl
+ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... @rd_rn_tszimm_shr
+LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... @rd_rn_tszimm_shr
+LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... @rd_rn_tszimm_shl
# SVE bitwise shift by wide elements (unpredicated)
# Note esz != 3
--
2.20.1
- [PATCH 07/31] target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated), (continued)
- [PATCH 07/31] target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated), Richard Henderson, 2020/03/26
- [PATCH 08/31] target/arm: Implement SVE2 integer halving add/subtract (predicated), Richard Henderson, 2020/03/26
- [PATCH 06/31] target/arm: Split out saturating/rounding shifts from neon, Richard Henderson, 2020/03/26
- [PATCH 09/31] target/arm: Implement SVE2 integer pairwise arithmetic, Richard Henderson, 2020/03/26
- [PATCH 10/31] target/arm: Implement SVE2 saturating add/subtract (predicated), Richard Henderson, 2020/03/26
- [PATCH 12/31] target/arm: Implement SVE2 integer add/subtract interleaved long, Richard Henderson, 2020/03/26
- [PATCH 11/31] target/arm: Implement SVE2 integer add/subtract long, Richard Henderson, 2020/03/26
- [PATCH 13/31] target/arm: Implement SVE2 integer add/subtract wide, Richard Henderson, 2020/03/26
- [PATCH 14/31] target/arm: Implement SVE2 integer multiply long, Richard Henderson, 2020/03/26
- [PATCH 15/31] target/arm: Implement PMULLB and PMULLT, Richard Henderson, 2020/03/26
- [PATCH 16/31] target/arm: Tidy SVE tszimm shift formats,
Richard Henderson <=
- [PATCH 17/31] target/arm: Implement SVE2 bitwise shift left long, Richard Henderson, 2020/03/26
- [PATCH 18/31] target/arm: Implement SVE2 bitwise exclusive-or interleaved, Richard Henderson, 2020/03/26
- [PATCH 19/31] target/arm: Implement SVE2 bitwise permute, Richard Henderson, 2020/03/26
- [PATCH 20/31] target/arm: Implement SVE2 complex integer add, Richard Henderson, 2020/03/26
- [PATCH 22/31] target/arm: Implement SVE2 integer add/subtract long with carry, Richard Henderson, 2020/03/26
- [PATCH 21/31] target/arm: Implement SVE2 integer absolute difference and accumulate long, Richard Henderson, 2020/03/26
- [PATCH 25/31] target/arm: Implement SVE2 bitwise shift right and accumulate, Richard Henderson, 2020/03/26
- [PATCH 29/31] target/arm: Vectorize SABD/UABD, Richard Henderson, 2020/03/26
- [PATCH 23/31] target/arm: Create arm_gen_gvec_[us]sra, Richard Henderson, 2020/03/26
- [PATCH 24/31] target/arm: Create arm_gen_gvec_{u,s}{rshr,rsra}, Richard Henderson, 2020/03/26