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Re: [PATCH v5 00/12] target/arm: Honor more HCR_EL2 traps
From: |
Peter Maydell |
Subject: |
Re: [PATCH v5 00/12] target/arm: Honor more HCR_EL2 traps |
Date: |
Mon, 2 Mar 2020 15:22:59 +0000 |
On Sat, 29 Feb 2020 at 01:28, Richard Henderson
<address@hidden> wrote:
>
> Changes for v5:
> * Patch 1 was broken for aa32. Not just the masking vs the "other"
> 32-bit register that Peter noticed, but more explicitly in that
> "ri" was dereferenced as NULL -- hcr_write{high,low} did not pass
> along the structure. Oops.
>
> Break out a new helper that is passed a starting mask, which is
> used to preserve bits from the "other" 32-bit register.
>
> Check the aa64 isar registers only if aarch64 is enabled.
>
> * Add HCR bits from armv8.6.
> * Remove EL2 & EL3 from user-only.
>
> * Mask hcr_el2 bits that are res0 in aa32.
> This didn't work at first because we weren't configuring SCR_RW
> for user-only, so aarch64-linux-user thought EL2 was aa32, which
> disabled pauth. Rather than find other corner cases like this,
> I think it makes more sense for user-only to only contend with EL1.
>
> Patches 1-5, 12 require review.
Applied to target-arm.next, thanks.
-- PMM
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