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Re: [PATCH v4 1/7] target/arm: Improve masking of HCR RES0 bits
From: |
Peter Maydell |
Subject: |
Re: [PATCH v4 1/7] target/arm: Improve masking of HCR RES0 bits |
Date: |
Fri, 28 Feb 2020 17:34:11 +0000 |
On Fri, 28 Feb 2020 at 16:57, Richard Henderson
<address@hidden> wrote:
>
> On 2/28/20 8:22 AM, Peter Maydell wrote:
> >> + if (ri->state == ARM_CP_STATE_AA32) {
> >> + /*
> >> + * Writes from aarch32 mode have more RES0 bits.
> >> + * This includes TDZ, RW, E2H, and more.
> >> + */
> >> + valid_mask &= ~0xff80ff8c90000000ull;
> >> + }
> >
> > Isn't bit HCR2 bit 16 (aka bit 32+16==48 here) also RES0 from AArch32 ?
>
> Yes, and it's set in the above.
One of us is miscounting, and I don't *think* it's me...
bits 63..0: ff80ff8c90000000
bits 63..32: ff80ff8c
bits 64..48: ff80
bit 48 looks like it's 0 to me.
> > I'm not really a fan of the hex-number here either, given we
> > have HCR_* constants.
>
> While plenty of those bits have names, many don't. Shall I simply name all of
> the ones that have names, and that differ from the aa64 masking?
You could refine the valid mask as the & of the bits which we
do want to exist in aarch32, rather than &~ of the reserved bits:
valid_mask &= TTLBIS | TOCU | TICAB | ...
?
thanks
-- PMM
[PATCH v4 2/7] target/arm: Honor the HCR_EL2.{TVM,TRVM} bits, Richard Henderson, 2020/02/25
[PATCH v4 3/7] target/arm: Honor the HCR_EL2.TSW bit, Richard Henderson, 2020/02/25
[PATCH v4 4/7] target/arm: Honor the HCR_EL2.TACR bit, Richard Henderson, 2020/02/25
[PATCH v4 5/7] target/arm: Honor the HCR_EL2.TPCP bit, Richard Henderson, 2020/02/25
[PATCH v4 6/7] target/arm: Honor the HCR_EL2.TPU bit, Richard Henderson, 2020/02/25