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[PATCH v2 01/21] target/arm: Add _aa32_ to isar_feature functions testin
From: |
Peter Maydell |
Subject: |
[PATCH v2 01/21] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers |
Date: |
Fri, 14 Feb 2020 17:50:56 +0000 |
Enforce a convention that an isar_feature function that tests a
32-bit ID register always has _aa32_ in its name, and one that
tests a 64-bit ID register always has _aa64_ in its name.
We already follow this except for three cases: thumb_div,
arm_div and jazelle, which all need _aa32_ adding.
(As noted in the comment, isar_feature_aa32_fp16_arith()
is an exception in that it currently tests ID_AA64PFR0_EL1,
but will switch to MVFR1 once we've properly implemented
FP16 for AArch32.)
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
v1->v2: fixed up new use of isar_feature_jazelle() in
aarch32_cpsr_valid_mask()
---
target/arm/cpu.h | 13 ++++++++++---
target/arm/internals.h | 2 +-
linux-user/elfload.c | 4 ++--
target/arm/cpu.c | 6 ++++--
target/arm/helper.c | 2 +-
target/arm/translate.c | 6 +++---
6 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index e943ffe8a9a..37d40e57901 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3324,20 +3324,27 @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *env,
unsigned regno)
/* Shared between translate-sve.c and sve_helper.c. */
extern const uint64_t pred_esz_masks[4];
+/*
+ * Naming convention for isar_feature functions:
+ * Functions which test 32-bit ID registers should have _aa32_ in
+ * their name. Functions which test 64-bit ID registers should have
+ * _aa64_ in their name.
+ */
+
/*
* 32-bit feature tests via id registers.
*/
-static inline bool isar_feature_thumb_div(const ARMISARegisters *id)
+static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
{
return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
}
-static inline bool isar_feature_arm_div(const ARMISARegisters *id)
+static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
{
return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
}
-static inline bool isar_feature_jazelle(const ARMISARegisters *id)
+static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
{
return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
}
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 58c4d707c5d..052449b4826 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1091,7 +1091,7 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t
features,
if ((features >> ARM_FEATURE_THUMB2) & 1) {
valid |= CPSR_IT;
}
- if (isar_feature_jazelle(id)) {
+ if (isar_feature_aa32_jazelle(id)) {
valid |= CPSR_J;
}
if (isar_feature_aa32_pan(id)) {
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index f3080a16358..b1a895f24ce 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -475,8 +475,8 @@ static uint32_t get_elf_hwcap(void)
GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3);
GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS);
GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4);
- GET_FEATURE_ID(arm_div, ARM_HWCAP_ARM_IDIVA);
- GET_FEATURE_ID(thumb_div, ARM_HWCAP_ARM_IDIVT);
+ GET_FEATURE_ID(aa32_arm_div, ARM_HWCAP_ARM_IDIVA);
+ GET_FEATURE_ID(aa32_thumb_div, ARM_HWCAP_ARM_IDIVT);
/* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.c.
* Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of
* ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index de733aceeb8..56f2ab865da 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1586,7 +1586,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
* Presence of EL2 itself is ARM_FEATURE_EL2, and of the
* Security Extensions is ARM_FEATURE_EL3.
*/
- assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(arm_div, cpu));
+ assert(!tcg_enabled() || no_aa32 ||
+ cpu_isar_feature(aa32_arm_div, cpu));
set_feature(env, ARM_FEATURE_LPAE);
set_feature(env, ARM_FEATURE_V7);
}
@@ -1612,7 +1613,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
if (arm_feature(env, ARM_FEATURE_V6)) {
set_feature(env, ARM_FEATURE_V5);
if (!arm_feature(env, ARM_FEATURE_M)) {
- assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(jazelle,
cpu));
+ assert(!tcg_enabled() || no_aa32 ||
+ cpu_isar_feature(aa32_jazelle, cpu));
set_feature(env, ARM_FEATURE_AUXCR);
}
}
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 366dbcf460d..eec3876610c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7396,7 +7396,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (arm_feature(env, ARM_FEATURE_LPAE)) {
define_arm_cp_regs(cpu, lpae_cp_reginfo);
}
- if (cpu_isar_feature(jazelle, cpu)) {
+ if (cpu_isar_feature(aa32_jazelle, cpu)) {
define_arm_cp_regs(cpu, jazelle_regs);
}
/* Slightly awkwardly, the OMAP and StrongARM cores need all of
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 20f89ace2fd..93f028f256b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -42,7 +42,7 @@
#define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5)
/* currently all emulated v5 cores are also v5TE, so don't bother */
#define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5)
-#define ENABLE_ARCH_5J dc_isar_feature(jazelle, s)
+#define ENABLE_ARCH_5J dc_isar_feature(aa32_jazelle, s)
#define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6)
#define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K)
#define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2)
@@ -9845,8 +9845,8 @@ static bool op_div(DisasContext *s, arg_rrr *a, bool u)
TCGv_i32 t1, t2;
if (s->thumb
- ? !dc_isar_feature(thumb_div, s)
- : !dc_isar_feature(arm_div, s)) {
+ ? !dc_isar_feature(aa32_thumb_div, s)
+ : !dc_isar_feature(aa32_arm_div, s)) {
return false;
}
--
2.20.1
- [PATCH v2 00/21] arm: ARMv8.1- and v8.4-PMU, ID reg cleanup, [H]ACTLR2, Peter Maydell, 2020/02/14
- [PATCH v2 01/21] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers,
Peter Maydell <=
- [PATCH v2 02/21] target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan, Peter Maydell, 2020/02/14
- [PATCH v2 04/21] target/arm: Define and use any_predinv isar_feature test, Peter Maydell, 2020/02/14
- [PATCH v2 03/21] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions, Peter Maydell, 2020/02/14
- [PATCH v2 07/21] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field, Peter Maydell, 2020/02/14
- [PATCH v2 05/21] target/arm: Factor out PMU register definitions, Peter Maydell, 2020/02/14
- [PATCH v2 08/21] target/arm: Define an aa32_pmu_8_1 isar feature test function, Peter Maydell, 2020/02/14
- [PATCH v2 06/21] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1, Peter Maydell, 2020/02/14
- [PATCH v2 12/21] target/arm: Read debug-related ID registers from KVM, Peter Maydell, 2020/02/14