Re: [PATCH] hw/arm/boot: Set NSACR.{CP11, CP10} in dummy SMC setup routine

[Bonnans, Laurent]

On 11/4/19 4:11 PM, Clement Deschamps wrote:

> Set the NSACR CP11 and CP10 bits, to allow FPU access in Non-Secure state
> when using dummy SMC setup routine. Otherwise an AArch32 kernel will UNDEF as
> soon as it tries to use the FPU.
>
> This fixes kernel panic when booting raspbian on raspi2.
I can confirm that it solves the kernel panics we've had in our tests 
when running our yocto-built images.

Tested-by: Laurent Bonnans <address@hidden>

Laurent
>
> Successfully tested with:
>    2017-01-11-raspbian-jessie-lite.img
>    2018-11-13-raspbian-stretch-lite.img
>    2019-07-10-raspbian-buster-lite.img
>
> See also commit ece628fcf6 that fixes the issue when *not* using the
> dummy SMC setup routine.
>
> Fixes: fc1120a7f5
> Signed-off-by: Clement Deschamps <address@hidden>
> ---
>   hw/arm/boot.c | 3 +++
>   1 file changed, 3 insertions(+)
>
> diff --git a/hw/arm/boot.c b/hw/arm/boot.c
> index ef6724960c..8fb4a63606 100644
> --- a/hw/arm/boot.c
> +++ b/hw/arm/boot.c
> @@ -240,6 +240,9 @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
>       };
>       uint32_t board_setup_blob[] = {
>           /* board setup addr */
> +        0xee110f51, /* mrc     p15, 0, r0, c1, c1, 2  ;read NSACR */
> +        0xe3800b03, /* orr     r0, #0xc00             ;set CP11, CP10 */
> +        0xee010f51, /* mcr     p15, 0, r0, c1, c1, 2  ;write NSACR */
>           0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */
>           0xee0c0f30, /* mcr     p15, 0, r0, c12, c0, 1 ;set MVBAR */
>           0xee110f11, /* mrc     p15, 0, r0, c1 , c1, 0 ;read SCR */