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Re: [PATCH 3/5] aspeed: Add a DRAM memory region at the SoC level
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From: |
Joel Stanley |
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Subject: |
Re: [PATCH 3/5] aspeed: Add a DRAM memory region at the SoC level |
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Date: |
Wed, 16 Oct 2019 11:24:40 +0000 |
On Wed, 16 Oct 2019 at 08:50, Cédric Le Goater <address@hidden> wrote:
>
> Currently, we link the DRAM memory region to the FMC model (for DMAs)
> through a property alias at the SoC level. The I2C model will need a
> similar region for DMA support, add a DRAM region property at the SoC
> level for both model to use.
>
> Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>