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Re: [Qemu-arm] [PATCH] KVM: arm/arm64: vgic: Allow more than 256 vcpus f
From: |
Peter Maydell |
Subject: |
Re: [Qemu-arm] [PATCH] KVM: arm/arm64: vgic: Allow more than 256 vcpus for KVM_IRQ_LINE |
Date: |
Tue, 3 Sep 2019 12:33:48 +0100 |
On Sun, 18 Aug 2019 at 15:07, Marc Zyngier <address@hidden> wrote:
>
> While parts of the VGIC support a large number of vcpus (we
> bravely allow up to 512), other parts are more limited.
>
> One of these limits is visible in the KVM_IRQ_LINE ioctl, which
> only allows 256 vcpus to be signalled when using the CPU or PPI
> types. Unfortunately, we've cornered ourselves badly by allocating
> all the bits in the irq field.
>
> Since the irq_type subfield (8 bit wide) is currently only taking
> the values 0, 1 and 2 (and we have been careful not to allow anything
> else), let's reduce this field to only 4 bits, and allocate the
> remaining 4 bits to a vcpu2_index, which acts as a multiplier:
>
> vcpu_id = 256 * vcpu2_index + vcpu_index
>
> With that, and a new capability (KVM_CAP_ARM_IRQ_LINE_LAYOUT_2)
> allowing this to be discovered, it becomes possible to inject
> PPIs to up to 4096 vcpus. But please just don't.
>
> Reported-by: Zenghui Yu <address@hidden>
> Signed-off-by: Marc Zyngier <address@hidden>
> diff --git a/Documentation/virt/kvm/api.txt b/Documentation/virt/kvm/api.txt
> index 2d067767b617..85518bfb2a99 100644
> --- a/Documentation/virt/kvm/api.txt
> +++ b/Documentation/virt/kvm/api.txt
> @@ -753,8 +753,8 @@ in-kernel irqchip (GIC), and for in-kernel irqchip can
> tell the GIC to
> use PPIs designated for specific cpus. The irq field is interpreted
> like this:
>
> - bits: | 31 ... 24 | 23 ... 16 | 15 ... 0 |
> - field: | irq_type | vcpu_index | irq_id |
> + bits: | 31 ... 28 | 27 ... 24 | 23 ... 16 | 15 ... 0 |
> + field: | vcpu2_index | irq_type | vcpu_index | irq_id |
>
> The irq_type field has the following values:
> - irq_type[0]: out-of-kernel GIC: irq_id 0 is IRQ, irq_id 1 is FIQ
> @@ -766,6 +766,10 @@ The irq_type field has the following values:
>
> In both cases, level is used to assert/deassert the line.
>
> +When KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 is supported, the target vcpu is
> +identified as (256 * vcpu2_index + vcpu_index). Otherwise, vcpu2_index
> +must be zero.
> +
> struct kvm_irq_level {
> union {
> __u32 irq; /* GSI */
> diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c
> index 35a069815baf..c1385911de69 100644
> --- a/virt/kvm/arm/arm.c
> +++ b/virt/kvm/arm/arm.c
> @@ -182,6 +182,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long
> ext)
> int r;
> switch (ext) {
> case KVM_CAP_IRQCHIP:
> + case KVM_CAP_ARM_IRQ_LINE_LAYOUT_2:
> r = vgic_present;
> break;
Shouldn't we be advertising the capability always, not just if
the VGIC is present? The KVM_IRQ_LINE ioctl can be used for
directly signalling IRQs to vCPUs even if we're using an
out-of-kernel irqchip model.
The general principle of the API change/extension looks OK to me.
thanks
-- PMM
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