Re: [Qemu-arm] [PATCH 13/67] target/arm: Convert Data Processing (reg, reg-shifted-reg, imm)

[Peter Maydell]

On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<address@hidden> wrote:
>
> Do these all in one lump because these are all logically intertwined.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  target/arm/translate.c | 747 ++++++++++++++++++++---------------------
>  target/arm/a32.decode  |  84 +++++
>  target/arm/t32.decode  |  91 +++++
>  3 files changed, 536 insertions(+), 386 deletions(-

I'm afraid this patch is too big for me to digest :-(

I just spent about half an hour trying to figure out whether
the changes just to the thumb dp-immediate insns were right
and didn't manage to work through it all.

> +
> +# Data-processing (immediate)
> +
> +%t32extrot       26:1 12:3 0:8  !function=t32_expandimm_rot
> +%t32extimm       26:1 12:3 0:8  !function=t32_expandimm_imm
> +
> +@s_rri_rot       ....... .... s:1 rn:4 . ... rd:4 ........ \
> +                 &s_rri_rot imm=%t32extimm rot=%t32extrot
> +@s_rxi_rot       ....... .... s:1 .... . ... rd:4 ........ \
> +                 &s_rri_rot imm=%t32extimm rot=%t32extrot rn=0
> +@S_xri_rot       ....... .... .   rn:4 . ... .... ........ \
> +                 &s_rri_rot imm=%t32extimm rot=%t32extrot s=1 rd=0
> +
> +{
> +  TST_rri        1111 0.0 0000 1 .... 0 ... 1111 ........     @S_xri_rot
> +  AND_rri        1111 0.0 0000 . .... 0 ... .... ........     @s_rri_rot
> +}
> +BIC_rri          1111 0.0 0001 . .... 0 ... .... ........     @s_rri_rot
> +{
> +  MOV_rri        1111 0.0 0010 . 1111 0 ... .... ........     @s_rxi_rot
> +  ORR_rri        1111 0.0 0010 . .... 0 ... .... ........     @s_rri_rot
> +}
> +{
> +  MVN_rri        1111 0.0 0011 . 1111 0 ... .... ........     @s_rxi_rot
> +  ORN_rri        1111 0.0 0011 . .... 0 ... .... ........     @s_rri_rot
> +}
> +{
> +  TEQ_rri        1111 0.0 0100 1 .... 0 ... 1111 ........     @S_xri_rot
> +  EOR_rri        1111 0.0 0100 . .... 0 ... .... ........     @s_rri_rot
> +}
> +{
> +  CMN_rri        1111 0.0 1000 1 .... 0 ... 1111 ........     @S_xri_rot
> +  ADD_rri        1111 0.0 1000 . .... 0 ... .... ........     @s_rri_rot
> +}
> +ADC_rri          1111 0.0 1010 . .... 0 ... .... ........     @s_rri_rot
> +SBC_rri          1111 0.0 1011 . .... 0 ... .... ........     @s_rri_rot
> +{
> +  CMP_rri        1111 0.0 1101 1 .... 0 ... 1111 ........     @S_xri_rot
> +  SUB_rri        1111 0.0 1101 . .... 0 ... .... ........     @s_rri_rot
> +}
> +RSB_rri          1111 0.0 1110 . .... 0 ... .... ........     @s_rri_rot
> --

Why do we split it up into all these different kinds of patterns
where some insns have special cases for rn==15 and some have
special cases for rd==15 ?
The legacy decoder doesn't seem to do that -- it treats everything
the same.

thanks
-- PMM