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[Qemu-arm] [PATCH 37/67] target/arm: Convert Unallocated memory hint
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH 37/67] target/arm: Convert Unallocated memory hint |
Date: |
Fri, 26 Jul 2019 10:50:02 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 8 --------
target/arm/a32-uncond.decode | 8 ++++++++
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 5366741d7b..87cbadc6cb 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10227,14 +10227,6 @@ static void disas_arm_insn(DisasContext *s, unsigned
int insn)
}
return;
}
- if (((insn & 0x0f700000) == 0x04100000) ||
- ((insn & 0x0f700010) == 0x06100000)) {
- if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) {
- goto illegal_op;
- }
- return; /* v7MP: Unallocated memory hint: must NOP */
- }
-
if ((insn & 0x0e000f00) == 0x0c000100) {
if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
/* iWMMXt register transfer. */
diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode
index aed381cb8e..afa95bf7aa 100644
--- a/target/arm/a32-uncond.decode
+++ b/target/arm/a32-uncond.decode
@@ -64,3 +64,11 @@ PLI 1111 0100 -101 ---- 1111 ---- ---- ----
# (imm, lit) 7
PLD 1111 0111 -101 ---- 1111 ----- -- 0 ---- # (register) 5te
PLDW 1111 0111 -001 ---- 1111 ----- -- 0 ---- # (register) 7mp
PLI 1111 0110 -101 ---- 1111 ----- -- 0 ---- # (register) 7
+
+# Unallocated memory hints
+#
+# Since these are v7MP nops, and PLDW is v7MP and implemented as nop,
+# (ab)use the PLDW helper.
+
+PLDW 1111 0100 -001 ---- ---- ---- ---- ----
+PLDW 1111 0110 -001 ---- ---- ---- ---0 ----
--
2.17.1
- [Qemu-arm] [PATCH 25/67] target/arm: Convert Parallel addition and subtraction, (continued)
- [Qemu-arm] [PATCH 25/67] target/arm: Convert Parallel addition and subtraction, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 27/67] target/arm: Convert Signed multiply, signed and unsigned divide, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 29/67] target/arm: Convert LDM, STM, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 30/67] target/arm: Convert B, BL, BLX (immediate), Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 31/67] target/arm: Convert SVC, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 33/67] target/arm: Convert Clear-Exclusive, Barriers, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 38/67] target/arm: Convert Table Branch, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 32/67] target/arm: Convert RFE and SRS, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 36/67] target/arm: Convert PLI, PLD, PLDW, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 35/67] target/arm: Convert SETEND, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 37/67] target/arm: Convert Unallocated memory hint,
Richard Henderson <=
- [Qemu-arm] [PATCH 34/67] target/arm: Convert CPS (privileged), Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 40/67] target/arm: Convert TT, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 41/67] target/arm: Simplify disas_thumb2_insn, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 43/67] target/arm: Add skeleton for T16 decodetree, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 39/67] target/arm: Convert SG, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 44/67] target/arm: Convert T16 data-processing (two low regs), Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 45/67] target/arm: Convert T16 load/store (register offset), Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 47/67] target/arm: Convert T16 add pc/sp (immediate), Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 48/67] target/arm: Convert T16 load/store multiple, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 46/67] target/arm: Convert T16 load/store (immediate offset), Richard Henderson, 2019/07/26