[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-arm] [PATCH 35/67] target/arm: Convert SETEND
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH 35/67] target/arm: Convert SETEND |
Date: |
Fri, 26 Jul 2019 10:50:00 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 22 +++++++++++++---------
target/arm/a32-uncond.decode | 4 ++++
2 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 8dbe189df7..1d07caa62a 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10135,6 +10135,18 @@ static bool trans_SB(DisasContext *s, arg_SB *a)
return true;
}
+static bool trans_SETEND(DisasContext *s, arg_SETEND *a)
+{
+ if (!ENABLE_ARCH_6) {
+ return false;
+ }
+ if (a->E != (s->be_data == MO_BE)) {
+ gen_helper_setend(cpu_env);
+ s->base.is_jmp = DISAS_UPDATE;
+ }
+ return true;
+}
+
/*
* Legacy decoder.
*/
@@ -10220,15 +10232,7 @@ static void disas_arm_insn(DisasContext *s, unsigned
int insn)
return; /* v7MP: Unallocated memory hint: must NOP */
}
- if ((insn & 0x0ffffdff) == 0x01010000) {
- ARCH(6);
- /* setend */
- if (((insn >> 9) & 1) != !!(s->be_data == MO_BE)) {
- gen_helper_setend(cpu_env);
- s->base.is_jmp = DISAS_UPDATE;
- }
- return;
- } else if ((insn & 0x0e000f00) == 0x0c000100) {
+ if ((insn & 0x0e000f00) == 0x0c000100) {
if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
/* iWMMXt register transfer. */
if (extract32(s->c15_cpar, 1, 1)) {
diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode
index eb1c55b330..d5ed48f0fd 100644
--- a/target/arm/a32-uncond.decode
+++ b/target/arm/a32-uncond.decode
@@ -24,6 +24,7 @@
&empty !extern
&i !extern imm
+&setend E
# Branch with Link and Exchange
@@ -50,3 +51,6 @@ DSB 1111 0101 0111 1111 1111 0000 0100 ----
DMB 1111 0101 0111 1111 1111 0000 0101 ----
ISB 1111 0101 0111 1111 1111 0000 0110 ----
SB 1111 0101 0111 1111 1111 0000 0111 0000
+
+# Set Endianness
+SETEND 1111 0001 0000 0001 0000 00 E:1 0 0000 0000 &setend
--
2.17.1
- [Qemu-arm] [PATCH 28/67] target/arm: Convert MOVW, MOVT, (continued)
- [Qemu-arm] [PATCH 28/67] target/arm: Convert MOVW, MOVT, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 25/67] target/arm: Convert Parallel addition and subtraction, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 27/67] target/arm: Convert Signed multiply, signed and unsigned divide, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 29/67] target/arm: Convert LDM, STM, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 30/67] target/arm: Convert B, BL, BLX (immediate), Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 31/67] target/arm: Convert SVC, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 33/67] target/arm: Convert Clear-Exclusive, Barriers, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 38/67] target/arm: Convert Table Branch, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 32/67] target/arm: Convert RFE and SRS, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 36/67] target/arm: Convert PLI, PLD, PLDW, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 35/67] target/arm: Convert SETEND,
Richard Henderson <=
- [Qemu-arm] [PATCH 37/67] target/arm: Convert Unallocated memory hint, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 34/67] target/arm: Convert CPS (privileged), Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 40/67] target/arm: Convert TT, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 41/67] target/arm: Simplify disas_thumb2_insn, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 43/67] target/arm: Add skeleton for T16 decodetree, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 39/67] target/arm: Convert SG, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 44/67] target/arm: Convert T16 data-processing (two low regs), Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 45/67] target/arm: Convert T16 load/store (register offset), Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 47/67] target/arm: Convert T16 add pc/sp (immediate), Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 48/67] target/arm: Convert T16 load/store multiple, Richard Henderson, 2019/07/26