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[Qemu-arm] [PATCH 33/67] target/arm: Convert Clear-Exclusive, Barriers
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH 33/67] target/arm: Convert Clear-Exclusive, Barriers |
Date: |
Fri, 26 Jul 2019 10:49:58 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 122 +++++++++++++++--------------------
target/arm/a32-uncond.decode | 10 +++
target/arm/t32.decode | 10 +++
3 files changed, 73 insertions(+), 69 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index b43b344f96..797e8f7344 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10049,6 +10049,58 @@ static bool trans_SRS(DisasContext *s, arg_SRS *a)
return true;
}
+/*
+ * Clear-Exclusive, Barriers
+ */
+
+static bool trans_CLREX(DisasContext *s, arg_CLREX *a)
+{
+ if (!ENABLE_ARCH_6K) {
+ return false;
+ }
+ gen_clrex(s);
+ return true;
+}
+
+static bool trans_DSB(DisasContext *s, arg_DSB *a)
+{
+ if (!s->thumb && !ENABLE_ARCH_7) {
+ return false;
+ }
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
+ return true;
+}
+
+static bool trans_DMB(DisasContext *s, arg_DMB *a)
+{
+ return trans_DSB(s, NULL);
+}
+
+static bool trans_ISB(DisasContext *s, arg_ISB *a)
+{
+ /*
+ * We need to break the TB after this insn to execute
+ * self-modifying code correctly and also to take
+ * any pending interrupts immediately.
+ */
+ gen_goto_tb(s, 0, s->pc & ~1);
+ return true;
+}
+
+static bool trans_SB(DisasContext *s, arg_SB *a)
+{
+ if (!dc_isar_feature(aa32_sb, s)) {
+ return false;
+ }
+ /*
+ * TODO: There is no speculation barrier opcode
+ * for TCG; MB and end the TB instead.
+ */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
+ gen_goto_tb(s, 0, s->pc & ~1);
+ return true;
+}
+
/*
* Legacy decoder.
*/
@@ -10142,38 +10194,6 @@ static void disas_arm_insn(DisasContext *s, unsigned
int insn)
s->base.is_jmp = DISAS_UPDATE;
}
return;
- } else if ((insn & 0x0fffff00) == 0x057ff000) {
- switch ((insn >> 4) & 0xf) {
- case 1: /* clrex */
- ARCH(6K);
- gen_clrex(s);
- return;
- case 4: /* dsb */
- case 5: /* dmb */
- ARCH(7);
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
- return;
- case 6: /* isb */
- /* We need to break the TB after this insn to execute
- * self-modifying code correctly and also to take
- * any pending interrupts immediately.
- */
- gen_goto_tb(s, 0, s->pc & ~1);
- return;
- case 7: /* sb */
- if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
- goto illegal_op;
- }
- /*
- * TODO: There is no speculation barrier opcode
- * for TCG; MB and end the TB instead.
- */
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
- gen_goto_tb(s, 0, s->pc & ~1);
- return;
- default:
- goto illegal_op;
- }
} else if ((insn & 0x0e000f00) == 0x0c000100) {
if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
/* iWMMXt register transfer. */
@@ -10636,43 +10656,7 @@ static void disas_thumb2_insn(DisasContext *s,
uint32_t insn)
gen_set_psr_im(s, offset, 0, imm);
}
break;
- case 3: /* Special control operations. */
- if (!arm_dc_feature(s, ARM_FEATURE_V7) &&
- !arm_dc_feature(s, ARM_FEATURE_M)) {
- goto illegal_op;
- }
- op = (insn >> 4) & 0xf;
- switch (op) {
- case 2: /* clrex */
- gen_clrex(s);
- break;
- case 4: /* dsb */
- case 5: /* dmb */
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
- break;
- case 6: /* isb */
- /* We need to break the TB after this insn
- * to execute self-modifying code correctly
- * and also to take any pending interrupts
- * immediately.
- */
- gen_goto_tb(s, 0, s->pc & ~1);
- break;
- case 7: /* sb */
- if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
- goto illegal_op;
- }
- /*
- * TODO: There is no speculation barrier opcode
- * for TCG; MB and end the TB instead.
- */
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
- gen_goto_tb(s, 0, s->pc & ~1);
- break;
- default:
- goto illegal_op;
- }
- break;
+ case 3: /* Special control operations, in decodetree */
case 4: /* bxj, in decodetree */
case 5: /* eret, in decodetree */
case 6: /* MRS, in decodetree */
diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode
index 3b961233e5..b077958cec 100644
--- a/target/arm/a32-uncond.decode
+++ b/target/arm/a32-uncond.decode
@@ -22,6 +22,7 @@
# All of those that have a COND field in insn[31:28] are in a32.decode
#
+&empty !extern
&i !extern imm
# Branch with Link and Exchange
@@ -37,3 +38,12 @@ BLX_i 1111 101 . ........................
&i imm=%imm24h
RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe
SRS 1111 110 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs
+
+# Clear-Exclusive, Barriers
+
+# QEMU does not require the option field for the barriers.
+CLREX 1111 0101 0111 1111 1111 0000 0001 1111
+DSB 1111 0101 0111 1111 1111 0000 0100 ----
+DMB 1111 0101 0111 1111 1111 0000 0101 ----
+ISB 1111 0101 0111 1111 1111 0000 0110 ----
+SB 1111 0101 0111 1111 1111 0000 0111 0000
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 26b51c3bb2..9fe1500fe0 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -306,6 +306,16 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ....
@rdm
# of the space is "reserved hint, behaves as nop".
NOP 1111 0011 1010 1111 1000 0000 ---- ----
}
+
+ # Miscelaneous control
+ {
+ CLREX 1111 0011 1011 1111 1000 1111 0010 1111
+ DSB 1111 0011 1011 1111 1000 1111 0100 ----
+ DMB 1111 0011 1011 1111 1000 1111 0101 ----
+ ISB 1111 0011 1011 1111 1000 1111 0110 ----
+ SB 1111 0011 1011 1111 1000 1111 0111 0000
+ }
+
# Note that the v7m insn overlaps both the normal and banked insn.
{
MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \
--
2.17.1
- [Qemu-arm] [PATCH 22/67] target/arm: Convert load/store (register, immediate, literal), (continued)
- [Qemu-arm] [PATCH 22/67] target/arm: Convert load/store (register, immediate, literal), Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 23/67] target/arm: Convert Synchronization primitives, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 24/67] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 26/67] target/arm: Convert Packing, unpacking, saturation, and reversal, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 28/67] target/arm: Convert MOVW, MOVT, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 25/67] target/arm: Convert Parallel addition and subtraction, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 27/67] target/arm: Convert Signed multiply, signed and unsigned divide, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 29/67] target/arm: Convert LDM, STM, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 30/67] target/arm: Convert B, BL, BLX (immediate), Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 31/67] target/arm: Convert SVC, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 33/67] target/arm: Convert Clear-Exclusive, Barriers,
Richard Henderson <=
- [Qemu-arm] [PATCH 38/67] target/arm: Convert Table Branch, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 32/67] target/arm: Convert RFE and SRS, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 36/67] target/arm: Convert PLI, PLD, PLDW, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 35/67] target/arm: Convert SETEND, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 37/67] target/arm: Convert Unallocated memory hint, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 34/67] target/arm: Convert CPS (privileged), Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 40/67] target/arm: Convert TT, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 41/67] target/arm: Simplify disas_thumb2_insn, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 43/67] target/arm: Add skeleton for T16 decodetree, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 39/67] target/arm: Convert SG, Richard Henderson, 2019/07/26