Re: [Qemu-arm] [PATCH v2 4/9] hw/block/pflash_cfi01: Start state machine as READY to accept commands

[John Snow]

On 7/1/19 8:12 PM, Philippe Mathieu-Daudé wrote:
> When the state machine is ready to accept command, the bit 7 of
> the status register (SR) is set to 1.
> The guest polls the status register and check this bit before
> writting command to the internal 'Write State Machine' (WSM).

writing

> 
> Set SR.7 bit to 1 when the device is created.
> 

Right, ok -- it looks like we don't set this on realize otherwise.
(Or if we do, it's not obvious where or how.)

> Reference: Read Array Flowchart
>   "Common Flash Interface (CFI) and Command Sets"
>    (Intel Application Note 646)
>    Appendix B "Basic Command Set"
> 
> Signed-off-by: Philippe Mathieu-Daudé <address@hidden>

Reviewed-by: John Snow <address@hidden>

> ---
>  hw/block/pflash_cfi01.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c
> index 33c77f6569..dd1dfd266b 100644
> --- a/hw/block/pflash_cfi01.c
> +++ b/hw/block/pflash_cfi01.c
> @@ -764,7 +764,7 @@ static void pflash_cfi01_realize(DeviceState *dev, Error 
> **errp)
>      }
>  
>      pflash_mode_read_array(pfl);
> -    pfl->status = 0;
> +    pfl->status = 0x80; /* WSM ready */
>      /* Hardcoded CFI table */
>      /* Standard "QRY" string */
>      pfl->cfi_table[0x10] = 'Q';
>