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Re: [Qemu-arm] [PATCH 17/19] aspeed/smc: add DMA calibration settings
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From: |
Joel Stanley |
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Subject: |
Re: [Qemu-arm] [PATCH 17/19] aspeed/smc: add DMA calibration settings |
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Date: |
Wed, 12 Jun 2019 01:40:56 +0000 |
On Sat, 25 May 2019 at 15:14, Cédric Le Goater <address@hidden> wrote:
>
> When doing calibration, the SPI clock rate in the CE0 Control Register
> and the read delay cycles in the Read Timing Compensation Register are
> set using bit[11:4] of the DMA Control Register.
>
> Signed-off-by: Cédric Le Goater <address@hidden>
Acked-by: Joel Stanley <address@hidden>
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