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[Qemu-arm] [PATCH 30/42] target/arm: Convert VNEG to decodetree
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH 30/42] target/arm: Convert VNEG to decodetree |
Date: |
Thu, 6 Jun 2019 18:45:57 +0100 |
Convert the VNEG instruction to decodetree.
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-vfp.inc.c | 10 ++++++++++
target/arm/translate.c | 6 +-----
target/arm/vfp.decode | 5 +++++
3 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index d0282f1f921..6e06b2a130a 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -1898,3 +1898,13 @@ static bool trans_VABS_dp(DisasContext *s, arg_VABS_dp
*a)
{
return do_vfp_2op_dp(s, gen_helper_vfp_absd, a->vd, a->vm);
}
+
+static bool trans_VNEG_sp(DisasContext *s, arg_VNEG_sp *a)
+{
+ return do_vfp_2op_sp(s, gen_helper_vfp_negs, a->vd, a->vm);
+}
+
+static bool trans_VNEG_dp(DisasContext *s, arg_VNEG_dp *a)
+{
+ return do_vfp_2op_dp(s, gen_helper_vfp_negd, a->vd, a->vm);
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index ace9f803ab7..cc67ab069bc 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -3098,7 +3098,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
return 1;
case 15:
switch (rn) {
- case 1:
+ case 1 ... 2:
/* Already handled by decodetree */
return 1;
default:
@@ -3112,7 +3112,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
/* rn is opcode, encoded as per VFP_SREG_N. */
switch (rn) {
case 0x00: /* vmov */
- case 0x02: /* vneg */
case 0x03: /* vsqrt */
break;
@@ -3291,9 +3290,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
case 0: /* cpy */
/* no-op */
break;
- case 2: /* neg */
- gen_vfp_neg(dp);
- break;
case 3: /* sqrt */
gen_vfp_sqrt(dp);
break;
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
index 7035861c270..79e41963be4 100644
--- a/target/arm/vfp.decode
+++ b/target/arm/vfp.decode
@@ -161,3 +161,8 @@ VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... \
vd=%vd_sp vm=%vm_sp
VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... \
vd=%vd_dp vm=%vm_dp
+
+VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... \
+ vd=%vd_sp vm=%vm_sp
+VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... \
+ vd=%vd_dp vm=%vm_dp
--
2.20.1
- [Qemu-arm] [PATCH 17/42] target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d, (continued)
- [Qemu-arm] [PATCH 17/42] target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 13/42] target/arm: Convert "single-precision" register moves to decodetree, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 11/42] target/arm: Add helpers for VFP register loads and stores, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 34/42] target/arm: Convert the VCVT-from-f16 insns to decodetree, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 42/42] target/arm: Fix short-vector increment behaviour, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 30/42] target/arm: Convert VNEG to decodetree,
Peter Maydell <=
- [Qemu-arm] [PATCH 14/42] target/arm: Convert VFP two-register transfer insns to decodetree, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 35/42] target/arm: Convert the VCVT-to-f16 insns to decodetree, Peter Maydell, 2019/06/06