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[Qemu-arm] [PATCH 06/26] target/arm: Decode FP instructions for M profil
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH 06/26] target/arm: Decode FP instructions for M profile |
Date: |
Tue, 16 Apr 2019 13:57:24 +0100 |
Correct the decode of the M-profile "coprocessor and
floating-point instructions" space:
* op0 == 0b11 is always unallocated
* if the CPU has an FPU then all insns with op1 == 0b101
are floating point and go to disas_vfp_insn()
For the moment we leave VLLDM and VLSTM as NOPs; in
a later commit we will fill in the proper implementation
for the case where an FPU is present.
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate.c | 26 ++++++++++++++++++++++----
1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index bb539111179..d280b3a9a3a 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -11727,10 +11727,19 @@ static void disas_thumb2_insn(DisasContext *s,
uint32_t insn)
case 6: case 7: case 14: case 15:
/* Coprocessor. */
if (arm_dc_feature(s, ARM_FEATURE_M)) {
- /* We don't currently implement M profile FP support,
- * so this entire space should give a NOCP fault, with
- * the exception of the v8M VLLDM and VLSTM insns, which
- * must be NOPs in Secure state and UNDEF in Nonsecure state.
+ /* 0b111x_11xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx */
+ if (extract32(insn, 24, 2) == 3) {
+ goto illegal_op; /* op0 = 0b11 : unallocated */
+ }
+
+ /*
+ * Decode VLLDM and VLSTM first: these are nonstandard because:
+ * * if there is no FPU then these insns must NOP in
+ * Secure state and UNDEF in Nonsecure state
+ * * if there is an FPU then these insns do not have
+ * the usual behaviour that disas_vfp_insn() provides of
+ * being controlled by CPACR/NSACR enable bits or the
+ * lazy-stacking logic.
*/
if (arm_dc_feature(s, ARM_FEATURE_V8) &&
(insn & 0xffa00f00) == 0xec200a00) {
@@ -11744,6 +11753,15 @@ static void disas_thumb2_insn(DisasContext *s,
uint32_t insn)
/* Just NOP since FP support is not implemented */
break;
}
+ if (arm_dc_feature(s, ARM_FEATURE_VFP) &&
+ ((insn >> 8) & 0xe) == 10) {
+ /* FP, and the CPU supports it */
+ if (disas_vfp_insn(s, insn)) {
+ goto illegal_op;
+ }
+ break;
+ }
+
/* All other insns: NOCP */
gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(),
default_exception_el(s));
--
2.20.1
- [Qemu-arm] [PATCH 00/26] target/arm: Implement M profile floating point, Peter Maydell, 2019/04/16
- [Qemu-arm] [PATCH 01/26] target/arm: Make sure M-profile FPSCR RES0 bits are not settable, Peter Maydell, 2019/04/16
- [Qemu-arm] [PATCH 02/26] hw/intc/armv7m_nvic: Allow reading of M-profile MVFR* registers, Peter Maydell, 2019/04/16
- [Qemu-arm] [PATCH 03/26] target/arm: Implement dummy versions of M-profile FP-related registers, Peter Maydell, 2019/04/16
- [Qemu-arm] [PATCH 04/26] target/arm: Disable most VFP sysregs for M-profile, Peter Maydell, 2019/04/16
- [Qemu-arm] [PATCH 06/26] target/arm: Decode FP instructions for M profile,
Peter Maydell <=
- [Qemu-arm] [PATCH 07/26] target/arm: Clear CONTROL_S.SFPA in SG insn if FPU present, Peter Maydell, 2019/04/16
- [Qemu-arm] [PATCH 08/26] target/arm: Handle SFPA and FPCA bits in reads and writes of CONTROL, Peter Maydell, 2019/04/16
- [Qemu-arm] [PATCH 09/26] target/arm/helper: don't return early for STKOF faults during stacking, Peter Maydell, 2019/04/16
- [Qemu-arm] [PATCH 05/26] target/arm: Honour M-profile FP enable bits, Peter Maydell, 2019/04/16
- [Qemu-arm] [PATCH 10/26] target/arm: Handle floating point registers in exception entry, Peter Maydell, 2019/04/16