I'm trying to create a new support machine to QEMU, the TMS570LC43 board, this board use the Cortex-R5f microcontroller.
At this moment when I do the "qemu-system-arm -M help" my machine is showed with the name "cortex-r5".
The probleme start when I try to instaciate the machine with the comand "qemu-system-arm --machine cortex-r5 -cpu cortex-r5f", after that I received the message "segmentation fault (core dump)".
#include "qemu/osdep.h"
#include "exec/address-spaces.h"
#include "qemu/error-report.h"
#include "hw/arm/cortex-R5.h"
//RTI -> Real Time Interruption
//static const uint32_t RTI_addr = 0xFFFFFC00;
static const uint32_t spi_addr[CR5_NUM_SPI] = {0xFFF7F400, 0xFFF7F600, 0xFFF7F800, 0xFFF7FA00, 0xFFF7FC00};
static const uint32_t i2c_addr[CR5_NUM_I2C] = {0xFFF7D400, 0xFFF7D500};
static const uint32_t can_addr[CR5_NUM_CAN] = {0XFFF7DC00, 0XFFF7DE00, 0X0FFF7E00, 0X0FFF7E200};
static const uint32_t adc_addr[CR5_NUM_ADC] = {0xFFF7C000, 0xFFF7C200};
static const uint32_t gio_addr[CR5_NUM_GIO] = {0xFFF7BC00};
Interrupt Request Assignement
http://www.ti.com/lit/ds/spns195c/spns195c.pdf
/* static const int rti_cmp_irq0 = 2;
static const int rti_cmp_irq1 = 3;
static const int rti_cmp_irq2 = 4;
static const int rti_cmp_irq3 = 5;
static const int rti_oflw_irq0 = 6;
static const int rti_oflw_irq1 = 7;
static const int rti_timebase_irq = 8; */
static const int spi_l0_irq[CR5_NUM_SPI] = {12, 17, 37, 49, 53};
static const int spi_l1_irq[CR5_NUM_SPI] = {26, 30, 38, 54, 56};
static const int i2c_irq[CR5_NUM_I2C] = {66, 114};
static const int can_l0_irq[CR5_NUM_CAN] = {16, 35, 45, 113};
static const int can_l1_irq[CR5_NUM_CAN] = {29, 42, 55, 117};
static const int can_if3_irq[CR5_NUM_CAN] = {44, 46, 60, 120};
static const int adc_swgroup1_irq[CR5_NUM_ADC] = {15, 51};
static const int adc_swgroup2_irq[CR5_NUM_ADC] = {28, 57};
static const int adc_eventgroup_irq[CR5_NUM_ADC] = {14, 50};
static const int adc_magnitudecmp_irq[CR5_NUM_ADC] = {31, 59};
static const int gio_high_irq[CR5_NUM_GIO] = {9};
static const int gio_low_irq[CR5_NUM_GIO] = {23};
static void cortexR5_initf(MachineState *mc)
CORTEXR5State *s = g_new0(CORTEXR5State, 1);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
//s->cr5_cpu = ARM_CPU(object_new(mc->cpu_type));
cpu = ARM_CPU(object_new(mc->cpu_type));
//object_initialize_child(obj, "cpu", &s->cr5_cpu, sizeof(s->cr5_cpu), ARM_CPU_TYPE_NAME("cortex-r5f"), &error_abort, NULL);
object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal);
memory_region_init_ram(flash, NULL, "CORTEXR5.flash", FLASH_SIZE, &error_fatal);
memory_region_init_alias(flash_alias, NULL, "CORTEXR5.flash.alias", flash, 0, FLASH_SIZE);
memory_region_set_readonly(flash, true);
memory_region_set_readonly(flash_alias, true);
memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
memory_region_add_subregion(system_memory, 0, flash_alias);
memory_region_init_ram(ram, NULL, "CORTEXR5.ram", SRAM_SIZE, &error_fatal);
memory_region_add_subregion(system_memory, RAM_BASE_ADDRESS, ram);
for (i = 0; i < CR5_NUM_SPI; i++)
dev = DEVICE(&(s->spi[i]));
object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
//error_propagate(errp, err);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, spi_addr[i]);
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(dev), spi_l0_irq[i]));
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(dev), spi_l1_irq[i]));
for (i = 0; i < CR5_NUM_I2C; i++)
dev = DEVICE(&(s->i2c[i]));
object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
//error_propagate(errp, err);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, i2c_addr[i]);
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(dev), i2c_irq[i]));
for (i = 0; i < CR5_NUM_CAN; i++)
dev = DEVICE(&(s->can[i]));
object_property_set_bool(OBJECT(&s->can[i]), true, "realized", &err);
//error_propagate(errp, err);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, can_addr[i]);
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(dev), can_l0_irq[i]));
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(dev), can_l1_irq[i]));
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(dev), can_if3_irq[i]));
object_property_set_int(OBJECT(s->adc_irqs), CR5_NUM_ADC, "num-lines", &err);
object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err);
//error_propagate(errp, err);
// qdev_connect_gpio_out(DEVICE(s->adc_irq), 0, qdev_get_gpio_in(dev));
for (i = 0; i < CR5_NUM_ADC; i++)
dev = DEVICE(&(s->adc[i]));
object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
//error_propagate(errp, err);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, adc_addr[i]);
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(dev), adc_swgroup1_irq[i]));
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(dev), adc_swgroup2_irq[i]));
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(dev), adc_eventgroup_irq[i]));
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(dev), adc_magnitudecmp_irq[i]));
for (i = 0; i < CR5_NUM_GIO; i++)
dev = DEVICE(&(s->gio[i]));
object_property_set_bool(OBJECT(&s->gio[i]), true, "realized", &err);
//error_propagate(errp, err);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, gio_addr[i]);
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(dev), gio_high_irq[i]));
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(dev), gio_low_irq[i]));
static void cortexR5_machine_init(MachineClass *mc){
//mc->name = "Cortex-R5f";
mc->desc = "Based on TMS570LC43x";
mc->init = cortexR5_initf;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r5f");