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[Qemu-arm] [PATCH 09/17] target/arm: Implement the SUBP instruction
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH 09/17] target/arm: Implement the SUBP instruction |
Date: |
Mon, 14 Jan 2019 12:11:14 +1100 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-a64.c | 24 ++++++++++++++++++++++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 6583ad93b1..98ff60c161 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5111,19 +5111,39 @@ static void handle_crc32(DisasContext *s,
*/
static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
{
- unsigned int sf, rm, opcode, rn, rd;
+ unsigned int sf, rm, opcode, rn, rd, setflag;
sf = extract32(insn, 31, 1);
+ setflag = extract32(insn, 29, 1);
rm = extract32(insn, 16, 5);
opcode = extract32(insn, 10, 6);
rn = extract32(insn, 5, 5);
rd = extract32(insn, 0, 5);
- if (extract32(insn, 29, 1)) {
+ if (setflag && opcode != 0) {
unallocated_encoding(s);
return;
}
switch (opcode) {
+ case 0: /* SUBP(S) */
+ if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
+ goto do_unallocated;
+ } else {
+ TCGv_i64 tcg_n, tcg_m, tcg_d;
+
+ tcg_n = read_cpu_reg_sp(s, rn, true);
+ tcg_m = read_cpu_reg_sp(s, rm, true);
+ tcg_gen_sextract_i64(tcg_n, tcg_n, 0, 55);
+ tcg_gen_sextract_i64(tcg_m, tcg_m, 0, 55);
+ tcg_d = cpu_reg(s, rd);
+
+ if (setflag) {
+ gen_sub_CC(true, tcg_d, tcg_n, tcg_m);
+ } else {
+ tcg_gen_sub_i64(tcg_d, tcg_n, tcg_m);
+ }
+ }
+ break;
case 2: /* UDIV */
handle_div(s, false, sf, rm, rn, rd);
break;
--
2.17.2
- [Qemu-arm] [PATCH 00/17] target/arm: Implement ARMv8.5-MemTag, Richard Henderson, 2019/01/13
- [Qemu-arm] [PATCH 01/17] target/arm: Add MTE_ACTIVE to tb_flags, Richard Henderson, 2019/01/13
- [Qemu-arm] [PATCH 02/17] target/arm: Extract TCMA with ARMVAParameters, Richard Henderson, 2019/01/13
- [Qemu-arm] [PATCH 03/17] target/arm: Add MTE system registers, Richard Henderson, 2019/01/13
- [Qemu-arm] [PATCH 04/17] target/arm: Fill in helper_mte_check, Richard Henderson, 2019/01/13
- [Qemu-arm] [PATCH 05/17] target/arm: Suppress tag check for sp+offset, Richard Henderson, 2019/01/13
- [Qemu-arm] [PATCH 06/17] target/arm: Implement the IRG instruction, Richard Henderson, 2019/01/13
- [Qemu-arm] [PATCH 07/17] target/arm: Implement ADDG, SUBG instructions, Richard Henderson, 2019/01/13
- [Qemu-arm] [PATCH 08/17] target/arm: Implement the GMI instruction, Richard Henderson, 2019/01/13
- [Qemu-arm] [PATCH 09/17] target/arm: Implement the SUBP instruction,
Richard Henderson <=
- [Qemu-arm] [PATCH 10/17] target/arm: Implement LDG, STG, ST2G instructions, Richard Henderson, 2019/01/13
- [Qemu-arm] [PATCH 11/17] target/arm: Implement the STGP instruction, Richard Henderson, 2019/01/13
- [Qemu-arm] [PATCH 12/17] target/arm: Implement the LDGV and STGV instructions, Richard Henderson, 2019/01/13
- [Qemu-arm] [PATCH 13/17] target/arm: Set PSTATE.TCO on exception entry, Richard Henderson, 2019/01/13
- [Qemu-arm] [PATCH 14/17] tcg: Introduce target-specific page data for user-only, Richard Henderson, 2019/01/13
- [Qemu-arm] [PATCH 15/17] target/arm: Add allocation tag storage for user-only, Richard Henderson, 2019/01/13
- [Qemu-arm] [PATCH 16/17] target/arm: Enable MTE, Richard Henderson, 2019/01/13
- [Qemu-arm] [PATCH 17/17] tests/tcg/aarch64: Add mte smoke tests, Richard Henderson, 2019/01/13