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[Qemu-arm] [PATCH v8 07/13] target-arm: Make PMCEID[01]_EL0 64 bit regis
From: |
Aaron Lindsay |
Subject: |
[Qemu-arm] [PATCH v8 07/13] target-arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23] |
Date: |
Tue, 20 Nov 2018 21:26:40 +0000 |
Signed-off-by: Aaron Lindsay <address@hidden>
---
target/arm/cpu.h | 4 ++--
target/arm/helper.c | 12 ++++++++++--
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 627e5c1995..50de58e4a2 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -837,8 +837,8 @@ struct ARMCPU {
uint32_t id_pfr0;
uint32_t id_pfr1;
uint32_t id_dfr0;
- uint32_t pmceid0;
- uint32_t pmceid1;
+ uint64_t pmceid0;
+ uint64_t pmceid1;
uint32_t id_afr0;
uint32_t id_mmfr0;
uint32_t id_mmfr1;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 71be6fb578..75f054fe79 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5432,7 +5432,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
{ .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
- .resetvalue = cpu->pmceid0 },
+ .resetvalue = extract64(cpu->pmceid0, 0, 32) },
+ { .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
+ .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
+ .resetvalue = extract64(cpu->pmceid0, 32, 32) },
{ .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
@@ -5440,7 +5444,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
{ .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
- .resetvalue = cpu->pmceid1 },
+ .resetvalue = extract64(cpu->pmceid1, 0, 32) },
+ { .name = "PMCEID3", .state = ARM_CP_STATE_AA32,
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
+ .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
+ .resetvalue = extract64(cpu->pmceid1, 32, 32) },
{ .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
--
2.19.1
- [Qemu-arm] [PATCH v8 00/13] More fully implement ARM PMUv3, Aaron Lindsay, 2018/11/20
- [Qemu-arm] [PATCH v8 01/13] migration: Add post_save function to VMStateDescription, Aaron Lindsay, 2018/11/20
- [Qemu-arm] [PATCH v8 02/13] target/arm: Reorganize PMCCNTR accesses, Aaron Lindsay, 2018/11/20
- [Qemu-arm] [PATCH v8 05/13] target/arm: Allow AArch32 access for PMCCFILTR, Aaron Lindsay, 2018/11/20
- [Qemu-arm] [PATCH v8 03/13] target/arm: Swap PMU values before/after migrations, Aaron Lindsay, 2018/11/20
- [Qemu-arm] [PATCH v8 06/13] target/arm: Implement PMOVSSET, Aaron Lindsay, 2018/11/20
- [Qemu-arm] [PATCH v8 04/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2018/11/20
- [Qemu-arm] [PATCH v8 07/13] target-arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23],
Aaron Lindsay <=
- [Qemu-arm] [PATCH v8 11/13] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2018/11/20
- [Qemu-arm] [PATCH v8 12/13] target/arm: Implement PMSWINC, Aaron Lindsay, 2018/11/20
- [Qemu-arm] [PATCH v8 08/13] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0, Aaron Lindsay, 2018/11/20
- [Qemu-arm] [PATCH v8 09/13] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Aaron Lindsay, 2018/11/20
- [Qemu-arm] [PATCH v8 13/13] target/arm: Send interrupts on PMU counter overflow, Aaron Lindsay, 2018/11/20