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Re: [Qemu-arm] [Qemu-devel] [PATCH 4/4] target/arm: Implement tailchaini
From: |
Richard Henderson |
Subject: |
Re: [Qemu-arm] [Qemu-devel] [PATCH 4/4] target/arm: Implement tailchaining for M profile cores |
Date: |
Fri, 20 Jul 2018 09:22:47 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 |
On 07/20/2018 07:56 AM, Peter Maydell wrote:
> Tailchaining is an optimization in handling of exception return
> for M-profile cores: if we are about to pop the exception stack
> for an exception return, but there is a pending exception which
> is higher priority than the priority we are returning to, then
> instead of unstacking and then immediately taking the exception
> and stacking registers again, we can chain to the pending
> exception without unstacking and stacking.
>
> For v6M and v7M it is IMPDEF whether tailchaining happens for pending
> exceptions; for v8M this is architecturally required. Implement it
> in QEMU for all M-profile cores, since in practice v6M and v7M
> hardware implementations generally do have it.
>
> (We were already doing tailchaining for derived exceptions which
> happened during exception return, like the validity checks and
> stack access failures; these have always been required to be
> tailchained for all versions of the architecture.)
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> target/arm/helper.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
Reviewed-by: Richard Henderson <address@hidden>
r~