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[Qemu-arm] [PATCH v5 05/13] target/arm: Remove redundant DIV detection f
From: |
Aaron Lindsay |
Subject: |
[Qemu-arm] [PATCH v5 05/13] target/arm: Remove redundant DIV detection for KVM |
Date: |
Fri, 22 Jun 2018 16:32:19 -0400 |
KVM implies V7VE, which implies ARM_DIV and THUMB_DIV. The conditional
detection here is therefore unnecessary. Because V7VE is already
unconditionally specified for all KVM hosts, ARM_DIV and THUMB_DIV are
already indirectly specified and do not need to be included here at all.
Signed-off-by: Aaron Lindsay <address@hidden>
---
target/arm/kvm32.c | 19 +------------------
1 file changed, 1 insertion(+), 18 deletions(-)
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index fb9ea37..4e91c11 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -36,7 +36,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* and then query that CPU for the relevant ID registers.
*/
int i, ret, fdarray[3];
- uint32_t midr, id_pfr0, id_isar0, mvfr1;
+ uint32_t midr, id_pfr0, mvfr1;
uint64_t features = 0;
/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
* we know these will only support creating one kind of guest CPU,
@@ -60,11 +60,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
},
{
.id = KVM_REG_ARM | KVM_REG_SIZE_U32
- | ENCODE_CP_REG(15, 0, 0, 0, 2, 0, 0),
- .addr = (uintptr_t)&id_isar0,
- },
- {
- .id = KVM_REG_ARM | KVM_REG_SIZE_U32
| KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1,
.addr = (uintptr_t)&mvfr1,
},
@@ -106,18 +101,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures
*ahcf)
set_feature(&features, ARM_FEATURE_VFP3);
set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
- switch (extract32(id_isar0, 24, 4)) {
- case 1:
- set_feature(&features, ARM_FEATURE_THUMB_DIV);
- break;
- case 2:
- set_feature(&features, ARM_FEATURE_ARM_DIV);
- set_feature(&features, ARM_FEATURE_THUMB_DIV);
- break;
- default:
- break;
- }
-
if (extract32(id_pfr0, 12, 4) == 1) {
set_feature(&features, ARM_FEATURE_THUMB2EE);
}
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
- [Qemu-arm] [PATCH v5 00/13] More fully implement ARM PMUv3, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 01/13] target/arm: Reorganize PMCCNTR accesses, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 03/13] target/arm: Allow AArch32 access for PMCCFILTR, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 02/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 04/13] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 05/13] target/arm: Remove redundant DIV detection for KVM,
Aaron Lindsay <=
- [Qemu-arm] [PATCH v5 06/13] target/arm: Implement PMOVSSET, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 07/13] target/arm: Add array for supported PMU events, generate PMCEID[01], Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 08/13] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 09/13] target/arm: PMU: Add instruction and cycle events, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 10/13] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 11/13] target/arm: Implement PMSWINC, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 13/13] target/arm: Send interrupts on PMU counter overflow, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 12/13] target/arm: Mark PMINTENSET accesses as possibly doing IO, Aaron Lindsay, 2018/06/22