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Re: [Qemu-arm] [PATCH v3 0/8] arm: implement TZ MPC
From: |
Peter Maydell |
Subject: |
Re: [Qemu-arm] [PATCH v3 0/8] arm: implement TZ MPC |
Date: |
Fri, 22 Jun 2018 11:06:08 +0100 |
On 20 June 2018 at 14:20, Peter Maydell <address@hidden> wrote:
> Hi; this is v3 of my iommu patchset. All the IOMMU stuff is now
> in master, so the remaining part is just implementing and using
> the Trustzone Memory Protection Controller in the mps2-an505.
>
> Changes from v2 to v3 (all fairly minor):
> * add new variable to clarify sense of LUT bits
> * only autoinc the IDX register if CTRL.AUTOINC is set
> * NS accesses should see IDregs only
> (The datasheet is unclear on the exact behaviour on an
> NS access to a non-ID register, so I've made a best guess
> and had them RAZ/WI. This behaviour is not reachable for
> the mps2-an505 anyway, so it doesn't really matter.)
Applied to target-arm.next, thanks.
-- PMM
- Re: [Qemu-arm] [PATCH v3 2/8] hw/misc/tz-mpc.c: Implement registers, (continued)
- [Qemu-arm] [PATCH v3 7/8] hw/arm/iotkit: Wire up MPC interrupt lines, Peter Maydell, 2018/06/20
- [Qemu-arm] [PATCH v3 1/8] hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller, Peter Maydell, 2018/06/20
- [Qemu-arm] [PATCH v3 6/8] hw/arm/iotkit: Instantiate MPC, Peter Maydell, 2018/06/20
- [Qemu-arm] [PATCH v3 5/8] hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUS, Peter Maydell, 2018/06/20
- [Qemu-arm] [PATCH v3 4/8] hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate, Peter Maydell, 2018/06/20
- [Qemu-arm] [PATCH v3 8/8] hw/arm/mps2-tz.c: Instantiate MPCs, Peter Maydell, 2018/06/20
- Re: [Qemu-arm] [Qemu-devel] [PATCH v3 0/8] arm: implement TZ MPC, no-reply, 2018/06/20
- Re: [Qemu-arm] [PATCH v3 0/8] arm: implement TZ MPC,
Peter Maydell <=