Re: [Qemu-arm] ARMv7-M MemManage vector trap

[Peter Maydell]

On 21 May 2018 at 16:31, Elliot Buller <address@hidden> wrote:
> I'm working on a body of code that relies heavily on the MPU faulting
> mechanism on cortex-m processors. This makes debugging other aspects
> difficult as GDB often traps in MPU fault while single stepping.
>
> On a real target it appears I can mask this by setting bit 4 of DEMCR (Debug
> Exception and Monitor Control Register). This looks to be unimplemented in
> QEMU. Does anyone have any ideas/guidance of where I should start looking to
> add support or another mechanism for disabling GDB trapping this ISR vector?

Is this gdb connected to QEMU's gdb stub?

DEMCR is part of the architectural support for halting debug. We
don't implement that, and our gdbstub doesn't work via halting
debug, so DEMCR is not what you're looking for.

I think that gdb-triggered accesses shouldn't actually cause us to generate
guest CPU exceptions (because the virt-to-phys calculation goes through
arm_cpu_get_phys_page_attrs_debug() and cpu_memory_rw_debug() rather than
the guest CPU's load/store codepaths). But it seems reasonable to me
that if the guest CPU can't read from an address then gdb reads should
also fail: this is how we handle it for other guest CPUs, I think.

thanks
-- PMM