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[Qemu-arm] [PATCH v2 04/14] target/arm: Clear SVE high bits for FMOV
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH v2 04/14] target/arm: Clear SVE high bits for FMOV |
Date: |
Wed, 2 May 2018 15:15:42 -0700 |
Use write_fp_dreg and clear_vec_high to zero the bits
that need zeroing for these cases.
Cc: address@hidden
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-a64.c | 17 +++++------------
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 7021a31b89..c64c3ed99d 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5444,31 +5444,24 @@ static void handle_fmov(DisasContext *s, int rd, int
rn, int type, bool itof)
if (itof) {
TCGv_i64 tcg_rn = cpu_reg(s, rn);
+ TCGv_i64 tmp;
switch (type) {
case 0:
- {
/* 32 bit */
- TCGv_i64 tmp = tcg_temp_new_i64();
+ tmp = tcg_temp_new_i64();
tcg_gen_ext32u_i64(tmp, tcg_rn);
- tcg_gen_st_i64(tmp, cpu_env, fp_reg_offset(s, rd, MO_64));
- tcg_gen_movi_i64(tmp, 0);
- tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd));
+ write_fp_dreg(s, rd, tmp);
tcg_temp_free_i64(tmp);
break;
- }
case 1:
- {
/* 64 bit */
- TCGv_i64 tmp = tcg_const_i64(0);
- tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_offset(s, rd, MO_64));
- tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd));
- tcg_temp_free_i64(tmp);
+ write_fp_dreg(s, rd, tcg_rn);
break;
- }
case 2:
/* 64 bit to top half. */
tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
+ clear_vec_high(s, true, rd);
break;
}
} else {
--
2.14.3
- [Qemu-arm] [PATCH v2 00/14] target/arm: Fixups for ARM_FEATURE_V8_FP16, Richard Henderson, 2018/05/02
- [Qemu-arm] [PATCH v2 01/14] target/arm: Implement vector shifted SCVF/UCVF for fp16, Richard Henderson, 2018/05/02
- [Qemu-arm] [PATCH v2 02/14] target/arm: Implement vector shifted FCVT for fp16, Richard Henderson, 2018/05/02
- [Qemu-arm] [PATCH v2 04/14] target/arm: Clear SVE high bits for FMOV,
Richard Henderson <=
- [Qemu-arm] [PATCH v2 03/14] target/arm: Fix float16 to/from int16, Richard Henderson, 2018/05/02
- [Qemu-arm] [PATCH v2 05/14] target/arm: Implement FMOV (general) for fp16, Richard Henderson, 2018/05/02
- [Qemu-arm] [PATCH v2 06/14] target/arm: Implement FCVT (scalar, integer) for fp16, Richard Henderson, 2018/05/02
- [Qemu-arm] [PATCH v2 07/14] target/arm: Implement FCVT (scalar, fixed-point) for fp16, Richard Henderson, 2018/05/02
- [Qemu-arm] [PATCH v2 09/14] target/arm: Implement FP data-processing (2 source) for fp16, Richard Henderson, 2018/05/02
- [Qemu-arm] [PATCH v2 14/14] target/arm: Fix sqrt_f16 exception raising, Richard Henderson, 2018/05/02
- [Qemu-arm] [PATCH v2 12/14] target/arm: Implement FCSEL for fp16, Richard Henderson, 2018/05/02
- [Qemu-arm] [PATCH v2 10/14] target/arm: Implement FP data-processing (3 source) for fp16, Richard Henderson, 2018/05/02