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[Qemu-arm] [PATCH 1/2] target/arm: Tidy conditions in handle_vec_simd_sh
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH 1/2] target/arm: Tidy conditions in handle_vec_simd_shri |
Date: |
Tue, 1 May 2018 11:04:54 -0700 |
The (size > 3 && !is_q) condition is identical to the preceeding test
of bit 3 in immh; eliminate it. For the benefit of Coverity, assert
that size is within the bounds we expect.
Fixes: Coverity CID1385846
Fixes: Coverity CID1385849
Fixes: Coverity CID1385852
Fixes: Coverity CID1385857
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-a64.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index bff4e13bf6..97950dce1a 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -9019,11 +9019,7 @@ static void handle_vec_simd_shri(DisasContext *s, bool
is_q, bool is_u,
unallocated_encoding(s);
return;
}
-
- if (size > 3 && !is_q) {
- unallocated_encoding(s);
- return;
- }
+ tcg_debug_assert(size <= 3);
if (!fp_access_check(s)) {
return;
--
2.14.3