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Re: [Qemu-arm] ARM memory barrier patch
From: |
Peter Maydell |
Subject: |
Re: [Qemu-arm] ARM memory barrier patch |
Date: |
Tue, 17 Apr 2018 22:51:51 +0100 |
On 17 April 2018 at 22:32, Henry Wertz <address@hidden> wrote:
> Please find submitted a patch for ARM memory barriers. This patch is
> against qemu-2.12-rc2 but I do believe it should apply for anything from
> 2.11.x to current. (the code being patched was added in for 2.11 series.)
>
>
> I found with qemu 2.11.x or newer that I would get an illegal instruction
> error running some Intel binaries on my ARM chromebook. On investigation,
> I found it was quitting on memory barriers.
> qemu instruction:
> mb $0x31
> was translating as:
> 0x604050cc: 5bf07ff5 blpl #0x600250a8
>
> After patch it gives:
> 0x604050cc: f57ff05b dmb ish
>
> In short, I found INSN_DMB_ISH (memory barrier for ARMv7) appeared to be
> correct based on online docs, but due to some endian-related shenanigans it
> had to be byte-swapped to suit qemu; it appears INSN_DMB_MCR (memory barrier
> for ARMv6) also should be byte swapped (and this patch does so).
> I have not checked for correctness of aarch64's barrier instruction.
>
> Signed-off-by: Henry Wertz <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Richard, did you want to take this via the tcg tree?
thanks
-- PMM