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Re: [Qemu-arm] [PATCH v3 06/22] target/arm: Mask PMU register writes bas
From: |
Peter Maydell |
Subject: |
Re: [Qemu-arm] [PATCH v3 06/22] target/arm: Mask PMU register writes based on PMCR_EL0.N |
Date: |
Thu, 12 Apr 2018 17:24:04 +0100 |
On 16 March 2018 at 20:31, Aaron Lindsay <address@hidden> wrote:
> This is in preparation for enabling counters other than PMCCNTR
>
> Signed-off-by: Aaron Lindsay <address@hidden>
> ---
> target/arm/helper.c | 24 +++++++++++++++---------
> 1 file changed, 15 insertions(+), 9 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 6480b80..5d5c738 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -52,11 +52,6 @@ typedef struct V8M_SAttributes {
> static void v8m_security_lookup(CPUARMState *env, uint32_t address,
> MMUAccessType access_type, ARMMMUIdx mmu_idx,
> V8M_SAttributes *sattrs);
> -
> -/* Definitions for the PMCCNTR and PMCR registers */
> -#define PMCRD 0x8
> -#define PMCRC 0x4
> -#define PMCRE 0x1
> #endif
>
> static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
> @@ -906,6 +901,17 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
> REGINFO_SENTINEL
> };
>
> +/* Definitions for the PMU registers */
> +#define PMCRN_MASK 0xf800
> +#define PMCRN_SHIFT 11
> +#define PMCRD 0x8
> +#define PMCRC 0x4
> +#define PMCRE 0x1
> +
> +#define PMU_NUM_COUNTERS(env) ((env->cp15.c9_pmcr & PMCRN_MASK) >>
> PMCRN_SHIFT)
> +/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
> +#define PMU_COUNTER_MASK(env) ((1 << 31) | ((1 << PMU_NUM_COUNTERS(env)) -
> 1))
These would be better as inline functions I think.
Otherwise
Reviewed-by: Peter Maydell <address@hidden>
thanks
-- PMM
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