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Re: [Qemu-arm] [PATCH v5 0/9] Add the ZynqMP PMU and IPI
From: |
Alistair Francis |
Subject: |
Re: [Qemu-arm] [PATCH v5 0/9] Add the ZynqMP PMU and IPI |
Date: |
Tue, 16 Jan 2018 15:31:29 -0800 |
On Tue, Jan 16, 2018 at 3:22 PM, Alistair Francis
<address@hidden> wrote:
>
> This series adds the ZynqMP Power Management Unit (PMU) machine with basic
> functionality.
>
> The machine only has the
> - CPU
> - Memory
> - Interrupt controller
> - IPI device
>
> connected, but that is enough to run some of the ROM and firmware
> code on the machine
>
> The series also adds the IPI device and connects it to the ZynqMP ARM
> side and the ZynqMP PMU. These IPI devices don't connect between the ARM
> and MicroBlaze instances though.
>
> V5:
> - Fix clang makecheck error
> - Rebase on master
> V4:
> - Rename the ZCU102 machine to just ZynqMP
> - Rename the PMC SoC to "xlnx,zynqmp-pmu-soc"
> - Move the IPI device to the machine instead of the SoC
> V3:
> - Add the interrupt controller
> - Replace some of the error_fatals with errp
> - Fix the PMU CPU name
>
>
>
> Alistair Francis (9):
> microblaze: boot.c: Don't try to find NULL pointer
> xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU
> xlnx-zynqmp-pmu: Add the CPU and memory
> aarch64-softmmu.mak: Use an ARM specific config
> xlnx-pmu-iomod-intc: Add the PMU Interrupt controller
> xlnx-zynqmp-pmu: Connect the PMU interrupt controller
> xlnx-zynqmp-ipi: Initial version of the Xilinx IPI device
> xlnx-zynqmp-pmu: Connect the IPI device to the PMU
> xlnx-zynqmp: Connect the IPI device to the ZynqMP SoC
>
> default-configs/aarch64-softmmu.mak | 1 +
> default-configs/microblaze-softmmu.mak | 1 +
> hw/arm/Makefile.objs | 2 +-
> hw/arm/xlnx-zynqmp.c | 14 +
> hw/display/Makefile.objs | 2 +-
> hw/dma/Makefile.objs | 1 +
> hw/intc/Makefile.objs | 2 +
> hw/intc/xlnx-pmu-iomod-intc.c | 554
> +++++++++++++++++++++++++++++++++
> hw/intc/xlnx-zynqmp-ipi.c | 377 ++++++++++++++++++++++
> hw/microblaze/Makefile.objs | 1 +
> hw/microblaze/boot.c | 2 +-
> hw/microblaze/xlnx-zynqmp-pmu.c | 204 ++++++++++++
> include/hw/arm/xlnx-zynqmp.h | 2 +
> include/hw/intc/xlnx-pmu-iomod-intc.h | 58 ++++
> include/hw/intc/xlnx-zynqmp-ipi.h | 57 ++++
> 15 files changed, 1275 insertions(+), 3 deletions(-)
> create mode 100644 hw/intc/xlnx-pmu-iomod-intc.c
> create mode 100644 hw/intc/xlnx-zynqmp-ipi.c
> create mode 100644 hw/microblaze/xlnx-zynqmp-pmu.c
> create mode 100644 include/hw/intc/xlnx-pmu-iomod-intc.h
> create mode 100644 include/hw/intc/xlnx-zynqmp-ipi.h
>
> --
> 2.14.1
>
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ARGH! Apparently Xilinx started this crap up again. I didn't realise
this is on all my emails. I'll work on getting it removed.
Alistair
- [Qemu-arm] [PATCH v5 1/9] microblaze: boot.c: Don't try to find NULL pointer, (continued)
- [Qemu-arm] [PATCH v5 1/9] microblaze: boot.c: Don't try to find NULL pointer, Alistair Francis, 2018/01/16
- [Qemu-arm] [PATCH v5 3/9] xlnx-zynqmp-pmu: Add the CPU and memory, Alistair Francis, 2018/01/16
- [Qemu-arm] [PATCH v5 4/9] aarch64-softmmu.mak: Use an ARM specific config, Alistair Francis, 2018/01/16
- [Qemu-arm] [PATCH v5 6/9] xlnx-zynqmp-pmu: Connect the PMU interrupt controller, Alistair Francis, 2018/01/16
- [Qemu-arm] [PATCH v5 5/9] xlnx-pmu-iomod-intc: Add the PMU Interrupt controller, Alistair Francis, 2018/01/16
- [Qemu-arm] [PATCH v5 7/9] xlnx-zynqmp-ipi: Initial version of the Xilinx IPI device, Alistair Francis, 2018/01/16
- [Qemu-arm] [PATCH v5 8/9] xlnx-zynqmp-pmu: Connect the IPI device to the PMU, Alistair Francis, 2018/01/16
- Re: [Qemu-arm] [PATCH v5 0/9] Add the ZynqMP PMU and IPI,
Alistair Francis <=