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Re: [Qemu-arm] [Qemu-devel] [PATCH 8/9] target/arm: Support some Thumb i
From: |
Richard Henderson |
Subject: |
Re: [Qemu-arm] [Qemu-devel] [PATCH 8/9] target/arm: Support some Thumb insns being always unconditional |
Date: |
Tue, 10 Oct 2017 19:52:42 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 |
On 10/09/2017 06:48 AM, Peter Maydell wrote:
> - if (dc->condexec_mask) {
> + if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) {
> uint32_t cond = dc->condexec_cond;
>
> if (cond != 0x0e) { /* Skip conditional when condition is AL. */
Don't you still need to advance the condexec_mask?
For HLT it doesn't matter, clearly.
I'm not sure what happens to an IT block for debug breakpoints.
But SG behaves as NOP when in non-secure memory.
That would seem to require that
itft eq
add r1, r0, r0
sg
add r2, r0, r0
add r3, r0, r0
should modify both r1 and r2 for T and r3 should be unconditional. If you
don't advance condexec_mask, it would seem that r2 gets F and r3 gets T.
r~
- [Qemu-arm] [PATCH 0/9] v8M: BLXNS, SG, secure function return, Peter Maydell, 2017/10/09
- [Qemu-arm] [PATCH 7/9] target-arm: Simplify insn_crosses_page(), Peter Maydell, 2017/10/09
- [Qemu-arm] [PATCH 6/9] target/arm: Pull Thumb insn word loads up to top level, Peter Maydell, 2017/10/09
- [Qemu-arm] [PATCH 9/9] target/arm: Implement SG instruction corner cases, Peter Maydell, 2017/10/09
- [Qemu-arm] [PATCH 3/9] target/arm: Implement BLXNS, Peter Maydell, 2017/10/09