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[Qemu-arm] [PATCH v1 12/12] target/arm: Decode aa32 armv8.3 2-reg-index
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH v1 12/12] target/arm: Decode aa32 armv8.3 2-reg-index |
Date: |
Wed, 4 Oct 2017 14:43:25 -0400 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 48f30e2621..50ef2f1f21 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7693,6 +7693,53 @@ static int disas_neon_insn_cp8_3same(DisasContext *s,
uint32_t insn)
return 0;
}
+/* ARMv8.3 reclaims a portion of the CDP2 coprocessor 8 space. */
+
+static int disas_neon_insn_cp8_index(DisasContext *s, uint32_t insn)
+{
+ int rd, rn, rm, rot, size, opr_sz;
+ TCGv_ptr fpst;
+ bool q;
+
+ /* FIXME: this access check should not take precedence over UNDEF
+ * for invalid encodings; we will generate incorrect syndrome information
+ * for attempts to execute invalid vfp/neon encodings with FP disabled.
+ */
+ if (s->fp_excp_el) {
+ gen_exception_insn(s, 4, EXCP_UDEF,
+ syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
+ return 0;
+ }
+ if (!s->vfp_enabled || !arm_dc_feature(s, ARM_FEATURE_V8_FCMA)) {
+ return 1;
+ }
+
+ q = extract32(insn, 6, 1);
+ size = extract32(insn, 23, 1);
+
+ if (size == 0) { /* FIXME: fp16 support */
+ return 1;
+ }
+
+ VFP_DREG_D(rd, insn);
+ VFP_DREG_N(rn, insn);
+ VFP_DREG_M(rm, insn);
+ if ((rd | rn) & q) {
+ return 1;
+ }
+
+ /* This entire space is VCMLA (indexed). */
+ rot = extract32(insn, 20, 2);
+ opr_sz = (1 + q) * 8;
+ fpst = get_fpstatus_ptr(1);
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
+ vfp_reg_offset(1, rn),
+ vfp_reg_offset(1, rm), fpst,
+ opr_sz, opr_sz, rot, gen_helper_gvec_fcmlas_idx);
+ tcg_temp_free_ptr(fpst);
+ return 0;
+}
+
static int disas_coproc_insn(DisasContext *s, uint32_t insn)
{
int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;
@@ -8414,6 +8461,12 @@ static void disas_arm_insn(DisasContext *s, unsigned int
insn)
goto illegal_op;
}
return;
+ } else if ((insn & 0x0f000f10) == 0x0e000800) {
+ /* ARMv8.3 neon cdp2 coprocessor 8 extension. */
+ if (disas_neon_insn_cp8_index(s, insn)) {
+ goto illegal_op;
+ }
+ return;
} else if ((insn & 0x0fe00000) == 0x0c400000) {
/* Coprocessor double register transfer. */
ARCH(5TE);
--
2.13.6
- [Qemu-arm] [PATCH v1 02/12] target/arm: Add ARM_FEATURE_V8_1_SIMD, (continued)
- [Qemu-arm] [PATCH v1 02/12] target/arm: Add ARM_FEATURE_V8_1_SIMD, Richard Henderson, 2017/10/04
- [Qemu-arm] [PATCH v1 03/12] target/arm: Decode aa64 armv8.1 scalar three same extra, Richard Henderson, 2017/10/04
- [Qemu-arm] [PATCH v1 05/12] target/arm: Decode aa64 armv8.1 scalar/vector x indexed element, Richard Henderson, 2017/10/04
- [Qemu-arm] [PATCH v1 04/12] target/arm: Decode aa64 armv8.1 three same extra, Richard Henderson, 2017/10/04
- [Qemu-arm] [PATCH v1 07/12] target/arm: Decode aa32 armv8.1 two reg and a scalar, Richard Henderson, 2017/10/04
- [Qemu-arm] [PATCH v1 08/12] target/arm: Add ARM_FEATURE_V8_FCMA, Richard Henderson, 2017/10/04
- [Qemu-arm] [PATCH v1 09/12] target/arm: Decode aa64 armv8.3 fcadd, Richard Henderson, 2017/10/04
- [Qemu-arm] [PATCH v1 06/12] target/arm: Decode aa32 armv8.1 three same, Richard Henderson, 2017/10/04
- [Qemu-arm] [PATCH v1 10/12] target/arm: Decode aa64 armv8.3 fcmla, Richard Henderson, 2017/10/04
- [Qemu-arm] [PATCH v1 11/12] target/arm: Decode aa32 armv8.3 3-same, Richard Henderson, 2017/10/04
- [Qemu-arm] [PATCH v1 12/12] target/arm: Decode aa32 armv8.3 2-reg-index,
Richard Henderson <=
- Re: [Qemu-arm] [Qemu-devel] [PATCH v1 00/12] ARM v8.1 simd + v8.3 complex insns, no-reply, 2017/10/04
- Re: [Qemu-arm] [Qemu-devel] [PATCH v1 00/12] ARM v8.1 simd + v8.3 complex insns, no-reply, 2017/10/04
- Re: [Qemu-arm] [Qemu-devel] [PATCH v1 00/12] ARM v8.1 simd + v8.3 complex insns, no-reply, 2017/10/04