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Re: [Qemu-arm] [PATCH 17/20] target/arm: Implement SG instruction
From: |
Peter Maydell |
Subject: |
Re: [Qemu-arm] [PATCH 17/20] target/arm: Implement SG instruction |
Date: |
Fri, 22 Sep 2017 18:18:26 +0100 |
On 22 September 2017 at 16:00, Peter Maydell <address@hidden> wrote:
> Implement the SG instruction, which we emulate 'by hand' in the
> exception handling code path.
I've just realised that this patch is correct as far as it goes
but it only implements the common path case for SG (where it is
in S&NSC memory and executed by a CPU in NS state). There is
also defined behaviour for:
* SG in NS memory (behaves as a NOP)
* SG in S memory and CPU already secure (clears IT bits and
does nothing else)
Those can be implemented in translate.c in the usual way;
I'll put a patch for that in the next set (or in a respin
of this set).
thanks
-- PMM
- [Qemu-arm] [PATCH 06/20] target/arm: Check for xPSR mismatch usage faults earlier for v8M, (continued)
- [Qemu-arm] [PATCH 06/20] target/arm: Check for xPSR mismatch usage faults earlier for v8M, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 03/20] target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 08/20] target/arm: Don't warn about exception return with PC low bit set for v8M, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 07/20] target/arm: Warn about restoring to unaligned stack, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 05/20] target/arm: Restore SPSEL to correct CONTROL register on exception return, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 10/20] target/arm: Update excret sanity checks for v8M, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 09/20] target/arm: Add new-in-v8M SFSR and SFAR, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 11/20] target/arm: Add support for restoring v8M additional state context, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 12/20] target/arm: Add v8M support to exception entry code, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 17/20] target/arm: Implement SG instruction, Peter Maydell, 2017/09/22
- Re: [Qemu-arm] [PATCH 17/20] target/arm: Implement SG instruction,
Peter Maydell <=
- [Qemu-arm] [PATCH 20/20] nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bit, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 02/20] target/arm: Don't switch to target stack early in v7M exception return, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 15/20] target/arm: Fix calculation of secure mm_idx values, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 13/20] nvic: Implement Security Attribution Unit registers, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 16/20] target/arm: Factor out "get mmuidx for specified security state", Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 14/20] target/arm: Implement security attribute lookups for memory accesses, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 18/20] target/arm: Implement BLXNS, Peter Maydell, 2017/09/22
- [Qemu-arm] [PATCH 19/20] target/arm: Implement secure function return, Peter Maydell, 2017/09/22