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[Qemu-arm] [PATCH 12/19] nvic: In escalation to HardFault, support HF no
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH 12/19] nvic: In escalation to HardFault, support HF not being priority -1 |
Date: |
Tue, 12 Sep 2017 19:13:59 +0100 |
When escalating to HardFault, we must go into Lockup if we
can't take the synchronous HardFault because the current
execution priority is already at or below the priority of
HardFault. In v7M HF is always priority -1 so a simple < 0
comparison sufficed; in v8M the priority of HardFault can
vary depending on whether it is a Secure or NonSecure
HardFault, so we must check against the priority of the
HardFault exception vector we're about to use.
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/armv7m_nvic.c | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 3361a28..c4670f7 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -487,18 +487,8 @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool
secure)
}
if (escalate) {
- if (running < 0) {
- /* We want to escalate to HardFault but we can't take a
- * synchronous HardFault at this point either. This is a
- * Lockup condition due to a guest bug. We don't model
- * Lockup, so report via cpu_abort() instead.
- */
- cpu_abort(&s->cpu->parent_obj,
- "Lockup: can't escalate %d to HardFault "
- "(current priority %d)\n", irq, running);
- }
- /* We can do the escalation, so we take HardFault instead.
+ /* We need to escalate this exception to a synchronous HardFault.
* If BFHFNMINS is set then we escalate to the banked HF for
* the target security state of the original exception; otherwise
* we take a Secure HardFault.
@@ -511,6 +501,17 @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool
secure)
} else {
vec = &s->vectors[irq];
}
+ if (running <= vec->prio) {
+ /* We want to escalate to HardFault but we can't take the
+ * synchronous HardFault at this point either. This is a
+ * Lockup condition due to a guest bug. We don't model
+ * Lockup, so report via cpu_abort() instead.
+ */
+ cpu_abort(&s->cpu->parent_obj,
+ "Lockup: can't escalate %d to HardFault "
+ "(current priority %d)\n", irq, running);
+ }
+
/* HF may be banked but there is only one shared HFSR */
s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
}
--
2.7.4
- Re: [Qemu-arm] [PATCH 02/19] nvic: Add banked exception states, (continued)
- [Qemu-arm] [PATCH 03/19] nvic: Add cached vectpending_is_s_banked state, Peter Maydell, 2017/09/12
- [Qemu-arm] [PATCH 04/19] nvic: Add cached vectpending_prio state, Peter Maydell, 2017/09/12
- [Qemu-arm] [PATCH 06/19] nvic: Make ICSR.RETTOBASE handle banked exceptions, Peter Maydell, 2017/09/12
- [Qemu-arm] [PATCH 05/19] nvic: Implement AIRCR changes for v8M, Peter Maydell, 2017/09/12
- [Qemu-arm] [PATCH 07/19] nvic: Implement NVIC_ITNS<n> registers, Peter Maydell, 2017/09/12
- [Qemu-arm] [PATCH 12/19] nvic: In escalation to HardFault, support HF not being priority -1,
Peter Maydell <=
- [Qemu-arm] [PATCH 10/19] nvic: Make SHPR registers banked, Peter Maydell, 2017/09/12
- [Qemu-arm] [PATCH 09/19] nvic: Make set_pending and clear_pending take a secure parameter, Peter Maydell, 2017/09/12
- [Qemu-arm] [PATCH 01/19] target/arm: Implement MSR/MRS access to NS banked registers, Peter Maydell, 2017/09/12
- [Qemu-arm] [PATCH 15/19] nvic: Handle v8M changes in nvic_exec_prio(), Peter Maydell, 2017/09/12
- [Qemu-arm] [PATCH 13/19] nvic: Implement v8M changes to fixed priority exceptions, Peter Maydell, 2017/09/12