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[Qemu-arm] [RFC PATCH 8/9] target/arm/helpers: introduce ADVSIMD flags
From: |
Alex Bennée |
Subject: |
[Qemu-arm] [RFC PATCH 8/9] target/arm/helpers: introduce ADVSIMD flags |
Date: |
Thu, 17 Aug 2017 19:04:03 +0100 |
This is used to pass constant information to the helper. This includes
immediate data and element counts/offsets.
Signed-off-by: Alex Bennée <address@hidden>
---
target/arm/advsimd_helper_flags.h | 50 +++++++++++++++++++++++++++++++++++++++
target/arm/helper-a64.c | 1 +
target/arm/translate-a64.c | 2 ++
3 files changed, 53 insertions(+)
create mode 100644 target/arm/advsimd_helper_flags.h
diff --git a/target/arm/advsimd_helper_flags.h
b/target/arm/advsimd_helper_flags.h
new file mode 100644
index 0000000000..47429e6fd1
--- /dev/null
+++ b/target/arm/advsimd_helper_flags.h
@@ -0,0 +1,50 @@
+/*
+ * AArch64 Vector Flags
+ *
+ * Copyright (c) 2017 Linaro
+ * Author: Alex Bennée <address@hidden>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* AdvSIMD element data
+ *
+ * We pack all the additional information for elements into a single
+ * 32 bit constant passed by register. Hopefully for groups of
+ * identical operations on different registers this should propergate
+ * nicely in the TCG.
+ *
+ * The following control element iteration:
+ * ADVSIMD_OPR_ELT - the count of elements affected
+ * ADVSIMD_ALL_ELT - the total count of elements (e.g. clear all-opr
elements)
+ * ADVSIMD_DOFF_ELT - the offset for the destination register (e.g. foo2 ops)
+ *
+ * We encode immediate data in:
+ * ADVSIMD_DATA
+ *
+ * Typically this is things like shift counts and the like.
+ */
+
+#define ADVSIMD_OPR_ELT_BITS 5
+#define ADVSIMD_OPR_ELT_SHIFT 0
+#define ADVSIMD_ALL_ELT_BITS 5
+#define ADVSIMD_ALL_ELT_SHIFT 5
+#define ADVSIMD_DOFF_ELT_BITS 5
+#define ADVSIMD_DOFF_ELT_SHIFT 10
+#define ADVSIMD_DATA_BITS 16
+#define ADVSIMD_DATA_SHIFT 16
+
+#define GET_SIMD_DATA(t, d) extract32(d, \
+ ADVSIMD_ ## t ## _SHIFT, \
+ ADVSIMD_ ## t ## _BITS)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index d9df82cff5..17b1edfb5f 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -30,6 +30,7 @@
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "qemu/int128.h"
+#include "advsimd_helper_flags.h"
#include "tcg.h"
#include <zlib.h> /* For crc32 */
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b5f48605a7..f474c5008b 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -34,6 +34,8 @@
#include "exec/helper-gen.h"
#include "exec/log.h"
+#include "advsimd_helper_flags.h"
+
#include "trace-tcg.h"
/* Global registers */
--
2.13.0
- [Qemu-arm] [RFC PATCH 4/9] helper-head: add support for vec type, (continued)
- [Qemu-arm] [RFC PATCH 4/9] helper-head: add support for vec type, Alex Bennée, 2017/08/17
- [Qemu-arm] [RFC PATCH 2/9] tcg: introduce the concepts of a TCGv_vec register type, Alex Bennée, 2017/08/17
- [Qemu-arm] [RFC PATCH 1/9] tcg/README: listify the TCG types., Alex Bennée, 2017/08/17
- [Qemu-arm] [RFC PATCH 9/9] target/arm/translate-a64: vectorise smull vD.4s, vN.[48]s, vM.h[], Alex Bennée, 2017/08/17
- [Qemu-arm] [RFC PATCH 7/9] target/arm/translate-a64: register global vectors, Alex Bennée, 2017/08/17
- [Qemu-arm] [RFC PATCH 6/9] target/arm/translate-a64: regnames -> x_regnames, Alex Bennée, 2017/08/17
- [Qemu-arm] [RFC PATCH 8/9] target/arm/helpers: introduce ADVSIMD flags,
Alex Bennée <=
- Re: [Qemu-arm] [Qemu-devel] [RFC PATCH 0/9] TCG Vector types and example conversion, no-reply, 2017/08/17
- Re: [Qemu-arm] [RFC PATCH 0/9] TCG Vector types and example conversion, Kirill Batuzov, 2017/08/18