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[Qemu-arm] [PATCH v3 4/5] aspeed: add a FTGMAC100 nic
From: |
Cédric Le Goater |
Subject: |
[Qemu-arm] [PATCH v3 4/5] aspeed: add a FTGMAC100 nic |
Date: |
Fri, 14 Apr 2017 10:35:02 +0200 |
There is a second NIC but we do not use it for the moment. We use the
'aspeed' property to tune the definition of the end of ring buffer bit
for the Aspeed SoCs.
Signed-off-by: Cédric Le Goater <address@hidden>
---
hw/arm/aspeed_soc.c | 21 +++++++++++++++++++++
include/hw/arm/aspeed_soc.h | 2 ++
2 files changed, 23 insertions(+)
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 571e4f097b02..4937e2bc8323 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -19,6 +19,7 @@
#include "hw/char/serial.h"
#include "qemu/log.h"
#include "hw/i2c/aspeed_i2c.h"
+#include "net/net.h"
#define ASPEED_SOC_UART_5_BASE 0x00184000
#define ASPEED_SOC_IOMEM_SIZE 0x00200000
@@ -33,6 +34,8 @@
#define ASPEED_SOC_TIMER_BASE 0x1E782000
#define ASPEED_SOC_WDT_BASE 0x1E785000
#define ASPEED_SOC_I2C_BASE 0x1E78A000
+#define ASPEED_SOC_ETH1_BASE 0x1E660000
+#define ASPEED_SOC_ETH2_BASE 0x1E680000
static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
@@ -175,6 +178,10 @@ static void aspeed_soc_init(Object *obj)
object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ASPEED_WDT);
object_property_add_child(obj, "wdt", OBJECT(&s->wdt), NULL);
qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default());
+
+ object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC100);
+ object_property_add_child(obj, "ftgmac100", OBJECT(&s->ftgmac100), NULL);
+ qdev_set_parent_bus(DEVICE(&s->ftgmac100), sysbus_get_default());
}
static void aspeed_soc_realize(DeviceState *dev, Error **errp)
@@ -299,6 +306,20 @@ static void aspeed_soc_realize(DeviceState *dev, Error
**errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, ASPEED_SOC_WDT_BASE);
+
+ /* Net */
+ qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]);
+ object_property_set_bool(OBJECT(&s->ftgmac100), true, "aspeed", &err);
+ object_property_set_bool(OBJECT(&s->ftgmac100), true, "realized",
+ &local_err);
+ error_propagate(&err, local_err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0, ASPEED_SOC_ETH1_BASE);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0,
+ qdev_get_gpio_in(DEVICE(&s->vic), 2));
}
static void aspeed_soc_class_init(ObjectClass *oc, void *data)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index dbec0c159885..4c5fc66a1ee0 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -20,6 +20,7 @@
#include "hw/i2c/aspeed_i2c.h"
#include "hw/ssi/aspeed_smc.h"
#include "hw/watchdog/wdt_aspeed.h"
+#include "hw/net/ftgmac100.h"
#define ASPEED_SPIS_NUM 2
@@ -39,6 +40,7 @@ typedef struct AspeedSoCState {
AspeedSMCState spi[ASPEED_SPIS_NUM];
AspeedSDMCState sdmc;
AspeedWDTState wdt;
+ FTGMAC100State ftgmac100;
} AspeedSoCState;
#define TYPE_ASPEED_SOC "aspeed-soc"
--
2.7.4
- [Qemu-arm] [PATCH v3 0/5] FTGMAC100 nic model for the Aspeed SoCs, Cédric Le Goater, 2017/04/14
- [Qemu-arm] [PATCH v3 1/5] hw/net: add MII definitions, Cédric Le Goater, 2017/04/14
- [Qemu-arm] [PATCH v3 2/5] net: add FTGMAC100 support, Cédric Le Goater, 2017/04/14
- [Qemu-arm] [PATCH v3 3/5] net/ftgmac100: add a 'aspeed' property, Cédric Le Goater, 2017/04/14
- [Qemu-arm] [PATCH v3 4/5] aspeed: add a FTGMAC100 nic,
Cédric Le Goater <=
- [Qemu-arm] [PATCH v3 5/5] slirp: add a fake NC-SI backend, Cédric Le Goater, 2017/04/14
- Re: [Qemu-arm] [PATCH v3 0/5] FTGMAC100 nic model for the Aspeed SoCs, Jason Wang, 2017/04/18