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Re: [Qemu-arm] [PATCH 10/23] target-arm: Expose output GPIO line for VCP
From: |
Edgar E. Iglesias |
Subject: |
Re: [Qemu-arm] [PATCH 10/23] target-arm: Expose output GPIO line for VCPU maintenance interrupt |
Date: |
Tue, 13 Dec 2016 13:37:26 +0100 |
User-agent: |
Mutt/1.5.24 (2015-08-30) |
On Tue, Dec 13, 2016 at 10:36:11AM +0000, Peter Maydell wrote:
> The GICv3 support for virtualization includes an outbound
> maintenance interrupt signal which is asserted when the
> CPU interface wants to signal to the hypervisor that it
> needs attention. Expose this as an outbound GPIO line from
> the CPU object which can be wired up as a physical interrupt
> line by the board code (as we do already for the CPU timers).
>
> Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
> ---
> target-arm/cpu.h | 2 ++
> target-arm/cpu.c | 3 +++
> 2 files changed, 5 insertions(+)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index ca5c849..c38488a 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -555,6 +555,8 @@ struct ARMCPU {
> QEMUTimer *gt_timer[NUM_GTIMERS];
> /* GPIO outputs for generic timer */
> qemu_irq gt_timer_outputs[NUM_GTIMERS];
> + /* GPIO output for GICv3 maintenance interrupt signal */
> + qemu_irq gicv3_maintenance_interrupt;
>
> /* MemoryRegion to use for secure physical accesses */
> MemoryRegion *secure_memory;
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 99f0dbe..5e0d21d 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -466,6 +466,9 @@ static void arm_cpu_initfn(Object *obj)
> arm_gt_stimer_cb, cpu);
> qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
> ARRAY_SIZE(cpu->gt_timer_outputs));
> +
> + qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
> + "gicv3-maintenance-interrupt", 1);
> #endif
>
> /* DTB consumers generally don't in fact care what the 'compatible'
> --
> 2.7.4
>
- [Qemu-arm] [PATCH 19/23] hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update(), (continued)
- [Qemu-arm] [PATCH 19/23] hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update(), Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 16/23] hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 21/23] hw/arm/virt: Support using SMC for PSCI, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 13/23] hw/intc/gicv3: Add defines for ICH system register fields, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 15/23] hw/intc/arm_gicv3: Add accessors for ICH_ system registers, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 08/23] hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 11/23] hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 23/23] hw/arm/virt: Add board property to enable EL2, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 10/23] target-arm: Expose output GPIO line for VCPU maintenance interrupt, Peter Maydell, 2016/12/13
- Re: [Qemu-arm] [PATCH 10/23] target-arm: Expose output GPIO line for VCPU maintenance interrupt,
Edgar E. Iglesias <=
- [Qemu-arm] [PATCH 07/23] hw/arm/virt: Don't incorrectly claim architectural timer to be edge-triggered, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 04/23] hw/arm/virt: add 2.9 machine type, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 05/23] hw/arm/virt: Merge VirtBoardInfo and VirtMachineState, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 02/23] hw/intc/arm_gicv3: Remove incorrect usage of fieldoffset, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 09/23] hw/intc/arm_gic: Add external IRQ lines for VIRQ and VFIQ, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 06/23] hw/arm/virt: Rename 'vbi' variables to 'vms', Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 03/23] hw/intc/arm_gicv3: Don't signal Pending+Active interrupts to CPU, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 01/23] target-arm: Log AArch64 exception returns, Peter Maydell, 2016/12/13