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[Qemu-arm] [PATCH v5 3/9] softfloat: For Mips only, correct order in pic
From: |
Aleksandar Markovic |
Subject: |
[Qemu-arm] [PATCH v5 3/9] softfloat: For Mips only, correct order in pickNaNMulAdd() |
Date: |
Mon, 18 Apr 2016 18:03:36 +0200 |
From: Aleksandar Markovic <address@hidden>
Only for Mips platform, and only for cases when snan_bit_is_one is 0,
correct the order of argument comparisons in pickNaNMulAdd().
For more info, see [2], page 53, section "3.5.3 NaN Propagation".
[1] "MIPS® Architecture For Programmers Volume II-A:
The MIPS64® Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015
[2] "MIPS Architecture for Programmers Volume IV-j:
The MIPS32® SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
fpu/softfloat-specialize.h | 41 +++++++++++++++++++++++++++++------------
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 093218f..11fc66b 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -571,19 +571,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag
bIsQNaN, flag bIsSNaN,
return 3;
}
- /* Prefer sNaN over qNaN, in the a, b, c order. */
- if (aIsSNaN) {
- return 0;
- } else if (bIsSNaN) {
- return 1;
- } else if (cIsSNaN) {
- return 2;
- } else if (aIsQNaN) {
- return 0;
- } else if (bIsQNaN) {
- return 1;
+ if (status->snan_bit_is_one) {
+ /* Prefer sNaN over qNaN, in the c, a, b order. */
+ if (cIsSNaN) {
+ return 2;
+ } else if (aIsSNaN) {
+ return 0;
+ } else if (bIsSNaN) {
+ return 1;
+ } else if (cIsQNaN) {
+ return 2;
+ } else if (aIsQNaN) {
+ return 0;
+ } else {
+ return 1;
+ }
} else {
- return 2;
+ /* Prefer sNaN over qNaN, in the a, b, c order. */
+ if (aIsSNaN) {
+ return 0;
+ } else if (bIsSNaN) {
+ return 1;
+ } else if (cIsSNaN) {
+ return 2;
+ } else if (aIsQNaN) {
+ return 0;
+ } else if (bIsQNaN) {
+ return 1;
+ } else {
+ return 2;
+ }
}
}
#elif defined(TARGET_PPC)
--
1.9.1
- Re: [Qemu-arm] [PATCH v5 5/9] target-mips: Activate IEEE 274-2008 signaling NaN bit meaning, (continued)
- [Qemu-arm] [PATCH v5 8/9] target-mips: Clean up position and order of helpers for CVT.<L|W>.<S|D>, Aleksandar Markovic, 2016/04/18
- [Qemu-arm] [PATCH v5 6/9] target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>, Aleksandar Markovic, 2016/04/18
- [Qemu-arm] [PATCH v5 4/9] target-mips: Amend processor definitions in relation to FCR31, Aleksandar Markovic, 2016/04/18
- [Qemu-arm] [PATCH v5 2/9] softfloat: For Mips only, correct default NaN values, Aleksandar Markovic, 2016/04/18
- [Qemu-arm] [PATCH v5 7/9] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>, Aleksandar Markovic, 2016/04/18
- [Qemu-arm] [PATCH v5 3/9] softfloat: For Mips only, correct order in pickNaNMulAdd(),
Aleksandar Markovic <=
- [Qemu-arm] [PATCH v5 9/9] target-mips: Clean up position of abs2008/nan2008 cases in genfarith(), Aleksandar Markovic, 2016/04/18
- [Qemu-arm] [PATCH v5 1/9] softfloat: Implement run-time-configurable meaning of signaling NaN bit, Aleksandar Markovic, 2016/04/18