Re: [Qemu-arm] [PATCH] target-arm: Fix and improve AA32 singlestep translation completion code

[Peter Maydell]

On 25 November 2015 at 18:02, Sergey Fedorov <address@hidden> wrote:
> The AArch32 translation completion code for singlestep enabled/active
> case was a way more confusing and too repetitive then it needs to be.
> Probably that was the cause for a bug to be introduced into it at some
> point. The bug was that SWI/HVC/SMC exception would be generated in
> condition-failed instruction code path whereas it shouldn't.
>
> This patch rewrites the code in a way similar to the non-singlestep
> case.
>
> In the condition-passed/unconditional instruction code path we need to:
>  - Write the condexec bits back to the CPU state
>  - Advance the singlestep state machine and generate a corresponding
>    exception in case of SWI/HVC/SMC
>  - Write the PC back to the CPU state if it hasn't already been written
>    and generate an appropriate singlestep exception otherwise
>
> In the condition-failed instruction code path we need to:
>  - Set a TCG label to jump to it if the condition is failed
>  - Write the condexec bits back to the CPU state
>  - Write the PC back to the CPU state since it hasn't been written in
>    this case
>  - Generate an appropriate singlestep exception
>
> Signed-off-by: Sergey Fedorov <address@hidden>

This looks much clearer than the code we had, and the parallel
between the singlestep code and the non-singlestep code is nice.

Applied to target-arm.next, thanks.

-- PMM