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Re: [Paparazzi-devel] HW


From: nisma
Subject: Re: [Paparazzi-devel] HW
Date: Tue, 25 May 2004 08:17:08 +0200 (MEST)

> Hi 
> 
> Quoting address@hidden:
> 
> > The proto PBC works.
> > The final design uses one 33 MIPS 186 CPU with USB host interfaces . and
> > other interfaces incl. support for WIFI and multimedia card (MMC).
> > If higher processing demand is required,  the PCU can be interfaced with
> > a gumstix CPU using the 13MB NSSP  interface (400 MH Xscale CPU with 64M
> > ram).
> 
> That looks nice. Can you give details about the cpu ? Which development
> environment is supported ? I understand the RF-datalink is managed by the
> 8bits MCUs ?
Go at http://www.gridconnect.com, it's the EX CPU.
256 Kb of internal ram, 512K or 2M external flash (rom).
For the developement tools, every C compiler for the 0x86 CPU with (or
without) optimisation for the 186 works. I recomment (all free) Watcom (best
code size and support for embedded runtime), Borland  an then GCC.
The RF-datalink can be managed by the 8bit MCU or by WIFI using the 16bit
CPU. Both solutions are possible.

> 
> > The servo controller and the RC receiver/modem interface are implemented
> > using microchip PIC MCU's. 
> 
> I really regret that there is no gcc support for these... Why do you
> prefer them
> over atmel MCUs ?
Cost,  implementation. HITECH has a free (2K limited) C compiler.
For the servo controller, atmel cpu can make the job. Pic controller simply
are cheaper. Other reasons are, that for pic MCU, there exists application
notes and reference implementations for brushless and brush speed
controllers and servo mixers including PC SW for modify the servo response
curve.
This reduces developement time.
I have made a servo controller with 2 indipendent speed controllers
including break (soft/hard/no), 6 servos , i2c + battery and motor RPM
monitoring.

The pic used for decoding the RC receiver are used to encode/decode 
modem modulation using the internal HW comparators / DA and free soft modem
implementation for en-/decoding up to 19200 bps.
I don't know any atmel implementation for this.

> 
> > This two cpu's can bypass the primary one.
> 
> What you mean bypass ? can you give details ? The way we are doing is
> described
> in these diagrams :
>
The servo controller, communication controller, analog controller, if any
are connected to the 186 CPU using multimaster I2C. This mean, that if
requested,
one of this MCU or even annother can go into multimaster I2C mode and 
ovverride any command issued by the master CPU.

http://savannah.nongnu.org/cgi-bin/viewcvs/paparazzi/paparazzi2/doc/user_manual/
> 
> We have one mega8 MCU (fly by wire) responsible for rc decoding and servos
> driving. It provides mixing and response curves for rc transmitter and
> servos.
I have it divided to two MCU, because i want to decode/encode data channel
with the MCU and have more  math power.
> Its ADCs are used for "health measurements" (like battery voltage) which
> can
> trigger low level actions (cut motor if battery low).
The servo controller make this. 
> This MCU alone is able to provide manual/automatic switching, manual
> control 
> and failsafe.
> The code is small and frozen. This is the critical part of the system.
The servo controller is external (different PBC) and optoisolated. It's no
problem using  you'r MEGA8 controller with I2C slave or RS232 interface.

> 
> The second MCU (autopilot) takes care of data acquisition/filtering,
> control,
> navigation, and communications (downlink only for now).
 > 
> 
> > What type of HW interfaces you need. Please give part number if
> possible.
> > Example are specialized SMD connectors for the GPS unit.
> 
> We use a SAM-LS GPS module. The connector is a flat ribbon 20 pins 0.5mm
> pitch.
> It is really fragile and we don't want these connector on our controller
> board.
> We build a small adapter board with the flat connector that we attach to
> the
> module. We use Molex 1.25mm pitch connector from there.
> 
> HTH
> 
> Antoine
> 
> > programmable gain amplifiers (PGA), analog multiplexers and so one.
> > The design uses BGA. This allow to use the newest parts with minimal
> space.
> > As example, the 186 CPU fit into a PBC layout or 14x20 mm having all the
> > necessary support logic (power, flash, ...) and external interfaces for
> > usb, ethernet, rs232 and others.
> > The primary reason to use this design/cpu is the usb host interface ,
> small
> > space, low cost and minimal support logic.
> > 
> > later
> > Chris
> > 
> > 
> > _______________________________________________
> > 
> > -- 
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> > 
> > 
> > 
> > _______________________________________________
> > Paparazzi-devel mailing list
> > address@hidden
> > http://mail.nongnu.org/mailman/listinfo/paparazzi-devel
> > 
> 
> 

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