(no subject)

[Jason D. York]

I am using GNU make for a project I am building under
DOS. I am looking for a good solution to get around
the 127 command line character limit. Unfortunately,
going to a new shell other than COMMAND.COM is not an
option for me.

So, I was looking through the MAKE manual for a
feature that is implemented some of the DOS make
programs that I have used in the past. In many of
them, you can put a set of delimiters around a section
of text and MAKE will write the contents to a
temporary file and replace the delimited string with
the file name.

For instance, if I had a variable set:
CCOPTS = -I ./include -I ./lib ... <exceeds 127 chars>

and then in my makefile, when I execute CC:
$(CC) $-o $@ -F!$(CCOPTS)!

The resolved string between the '!' chars would be
written to a temp file and the string would be
replaced with a filename.

The -F parameter reads additional parameters from
specified file (obviously.)

Is there any comparable feature in GNU MAKE that I am
overlooking? If not, are there any plans to implement
such a feature? I think it would be very useful.

Any Ideas would be appreciated.

Thank you,
  -- Jason York



_________________________________________________________
Do You Yahoo!?
Get your free @yahoo.com address at http://mail.yahoo.com